概率计算及混合概率计算

李洪革; 陈宇昊; 吴俊毅; 宋印杰; 朱新宇

doi:10.12263/DZXB.20230222

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概率计算及混合概率计算

学术论文 | 更新时间：2025-12-11

- 概率计算及混合概率计算
- Stochastic Computing and Hybrid Stochastic Computing
- 电子学报 2024年52卷第2期页码：428-440
- 作者机构：
  
  北京航空航天大学电子信息工程学院，北京市 100191
- 作者简介：
  
  [ "李洪革男.2005年获得日本东北大学信息科学研究院的工学博士学位.2006年至2008年，在日本东北大学生物智能机器人系担任助理教授.现任北京航空航天大学电子信息工程学院教授、博导.主要研究方向为智能（概率）计算、显示驱动/触控芯片、芯片安全及电磁干扰等实时混合系统的信号处理及片上设计领域的交叉.已经发表期刊和国际会议等学术论文100余篇，已授权专利15项. E-mail: honggeli@buaa.edu.cn" ]
  [ "陈宇昊男.2019年获得北京航空航天大学电子信息工程学院的学士学位.现为北京航空航天大学电子信息工程学院博士研究生.主要研究方向为概率计算、神经形态计算." ]
  [ "吴俊毅男.2023年获得北京航空航天大学高等理工学院的学士学位.现为北京航空航天大学电子信息工程学院硕士研究生.主要研究方向为低功耗数字电路设计、概率计算. E-mail: zy2302410@buaa.edu.cn" ]
  [ "宋印杰男.2021年获得北京航空航天大学高等理工学院的学士学位.现为北京航空航天大学电子信息工程学院博士研究生.主要研究方向包括数字集成电路、密码芯片设计. E-mail: yinjiesong@buaa.edu.cn" ]
  [ "朱新宇男.2020年获得合肥工业大学微电子学院的硕士学位.现为北京航空航天大学电子信息工程学院博士研究生.主要研究方向为异构多核处理器SoC设计、神经网络专用芯片. E-mail: zxyuser@buaa.edu.cn" ]
- 基金信息：
  
  国家自然科学基金(62071019)
- DOI：10.12263/DZXB.20230222
  中图分类号： TP391;
- 收稿：2023-03-09，
  
  修回：2023-06-30，
  
  纸质出版：2024-02-25
- 稿件说明：
移动端阅览
李洪革,陈宇昊,吴俊毅,等.概率计算及混合概率计算[J].电子学报,2024,52(02):428-440.

LI Hong-ge, CHEN Yu-hao, WU Jun-yi, et al.Stochastic Computing and Hybrid Stochastic Computing[J].Acta Electronica Sinica, 2024, 52(02): 428-440.
李洪革,陈宇昊,吴俊毅,等.概率计算及混合概率计算[J].电子学报,2024,52(02):428-440. DOI：10.12263/DZXB.20230222

LI Hong-ge, CHEN Yu-hao, WU Jun-yi, et al.Stochastic Computing and Hybrid Stochastic Computing[J].Acta Electronica Sinica, 2024, 52(02): 428-440. DOI：10.12263/DZXB.20230222

摘要

非位置概率数的计算机制已经成为边缘计算片上系统的新范式.本文介绍了概率计算（stochastic computing）的起源、发展和目前国内外的研究现状.针对传统概率计算存在诸如计算时延长、脉冲串信息携带效率低等问题，本文提出了二进制数-概率脉冲串混合编码的混合概率数概念，并从数的表示机理上阐释了二进制数、概率数和混合概率数的数理关系，进而揭示了混合概率计算所具备的低时延、高算力和高能效比的计算特点.本文基于40 nm CMOS工艺设计混合概率深度神经网络，该神经网络芯片在内核面积仅0.73 mm × 0.73 mm的条件下，设计4 544个乘累加（MAC）单元.在时钟频率400 MHz条件下，总功率为102.3 mW，其中动态功耗仅97 μW.通过ASIC芯片的实验测试表明，混合概率计算作为一种全新的颠覆性计算范式，与其他确定性、可扩展和全并行等概率计算方案相比，其能效比分别提高了50倍、2.5倍和3.26倍.

Abstract

The calculation principle of non-positional stochastic number (SN) is a promising technique for realizing high-performance computing owing to its extremely low hardware cost. This paper introduces detailly the origin

development process and the domestic and foreign development present situation. However

a disadvantage of stochastic bitstream is that the computing latency

and information-carrying efficiency and so on. We presented a hybrid stochastic computing (HSC) based on a hybrid bitstream to solve these problems

which achieves a lower hardware cost

better accuracy

and faster speed. The HSC neural networks is fabricated by 40 nm low-power CMOS process

with a core area of 0.73 mm × 0.73 mm

power of 102.3 mW and clock of 400 MHz

which has 4 544 multiply and accumulation (MAC).The proposed Hybrid stochastic computing is tested by FPGA and ASIC.Compared with other stochastic computing method

the method proposed gains 50×

2.5×

and 3.26× energy efficiency than other methods of traditional stochastic computing.

关键词

Keywords

references

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