国防科技大学,湖南长沙 410073
[ "张 庚 男,1994年12月出生于北京平谷.目前就读于国防科技大学,在读博士研究生.主要研究方向为高速SerDes串口技术.E-mail: zhanggeng23@nudt.edu.cn" ]
[ "赖明澈 男,1982年出生于湖北省.教授,博士生导师.主要研究方向为计算机体系结构、高性能互连网络、高速光电集成电路.E-mail: mingchelai@nudt.edu.cn" ]
[ "吕方旭 男,1988年出生于陕西省.副研究员.现就职于中国湖南国防科技大学计算机科学学院.主要研究方向为高速串口系统设计." ]
[ "齐星云 1979年出生于陕西省.分别于2001年、2003年和2009年获得国防科技大学学士学位、硕士学位和博士学位.硕士生导师.主要研究方向为高性能计算机体系结构、高速互连、ASIC芯片设计.E-mail: qi_xingyun@nudt.edu.cn" ]
[ "王 强 男,山东泗水人.博士,助理研究员.研究方向为计算机系统结构、高速互连网络和人工智能.E-mail: qiangwang@nudt.edu.cn" ]
[ "许超龙 男,1988年出生于湖南省岳阳市.目前为国防科技大学计算机科学专业博士研究生.主要研究方向为高速信号处理、互连技术和微电子技术.E-mail: xcl@nudt.edu.cn" ]
[ "李 萌 男.计算机科学与技术专业在读硕士研究生.研究方向为ADC.E-mail: lmengnudt@nudt.edu.cn" ]
[ "任博琳 男,2020年出生于河北省邢台市.硕士研究生.研究方向为高速串行接口.E-mail: genius@uestc.edu.cn" ]
收稿:2023-04-21,
修回:2023-09-15,
纸质出版:2024-08-25
移动端阅览
张庚, 赖明澈, 吕方旭, 等. 基于7阶相关NRZ编码的D2D接口设计[J]. 电子学报, 2024, 52(08): 2688-2705.
ZHANG Geng, LAI Ming-che, LÜ Fang-xu, et al. Design of D2D Interface Based on 7-Order Correlated NRZ Coding[J]. Acta Electronica Sinica, 2024, 52(08): 2688-2705.
张庚, 赖明澈, 吕方旭, 等. 基于7阶相关NRZ编码的D2D接口设计[J]. 电子学报, 2024, 52(08): 2688-2705. DOI:10.12263/DZXB.20230360
ZHANG Geng, LAI Ming-che, LÜ Fang-xu, et al. Design of D2D Interface Based on 7-Order Correlated NRZ Coding[J]. Acta Electronica Sinica, 2024, 52(08): 2688-2705. DOI:10.12263/DZXB.20230360
本文提出了一种新型高带宽密度、低功耗的面向片上(Die to Die,D2D)互连的7阶相关非归零(Non-Return-to-Zero,NRZ)编码接口电路结构.为了进一步提高5阶相关NRZ编码在D2D互连中的信噪比和带宽密度,设计了基于发射矩阵和接收矩阵的编解码电路.基于发射矩阵,在发射端设计了基于电压模驱动的编码电路,有效降低了功耗;基于接收矩阵,在接收端设计了基于有源可调电感的解码均衡电路,提高了通信速率.同时,为了解决接收端时钟偏斜问题,还设计了误码校准电路.该接口电路采用28 nm CMOS(Complementary Metal Oxide Semiconductor)工艺设计,核心面积为3 mm
2
,可适用于10~50 mm的片上互连.后端仿真结果表明,在奈奎斯特频率为20 GHz、信道插损为-8 dB的条件下,接收端最窄眼宽为0.45 UI,误码率小于
<math id="M1"><msup><mrow><mn mathvariant="normal">10</mn></mrow><mrow><mo>-</mo><mn mathvariant="normal">15</mn></mrow></msup></math>
https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=94325125&type=
2.53999996
https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=94325126&type=
5.92666674
,能耗效率为1.2 pJ/b,带宽密度为448 Gbps/mm.
In this paper
a novel high-bandwidth density and low-power 7-order correlated NRZ (Non-Return-to-Zero) coding interface circuit for D2D (Die to Die) interconnection is proposed. In order to further improve the SNR (signal-to-noise ratio) and bandwidth density of 5-order correlated NRZ coding
this paper designs encoding and decoding circuits based on transmission and reception matrices. Based on the transmission matrix
a voltage-mode encoding circuit is designed at the transmitti
ng end to effectively reduce power consumption. Based on the reception matrix
a decoding equalization circuit based on active adjustable inductor is designed at the receiving end to improve communication speed. In order to solve the problem of clock skew at the receiving end
this paper also designs an error correction circuit. The interface circuit is designed using 28 nm CMOS (Complementary Metal Oxide Semiconductor) technology
with a core area of 3 mm
2
and can be applied to on-chip interconnects ranging from 10 to 50 mm. The backend simulation results indicate that
under the condition of a Nyquist frequency of 20 GHz and a channel loss of -8 dB
the receiver's narrowest eye width is 0.45 UI
with a bit error rate less than
<math id="M2"><msup><mrow><mn mathvariant="normal">10</mn></mrow><mrow><mo>-</mo><mn mathvariant="normal">15</mn></mrow></msup></math>
https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=94325158&type=
2.53999996
https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=94325137&type=
5.92666674
energy efficiency of 1.2 pJ/b
and bandwidth density of 448 Gbps/mm.
LI T , HOU J , YAN J L , et al . Chiplet heterogeneous integration technology—Status and challenges [J ] . Electronics , 2020 , 9 ( 4 ): 670 .
杨晖 . 后摩尔时代Chiplet技术的演进与挑战 [J ] . 集成电路应用 , 2020 , 37 ( 5 ): 52 - 54 .
YANG H . Evolution and challenge of Chiplet in more Moore [J ] . Application of IC , 2020 , 37 ( 5 ): 52 - 54 . (in Chinese)
陈桂林 , 王观武 , 胡健 , 等 . Chiplet封装结构与通信结构综述 [J ] . 计算机研究与发展 , 2022 , 59 ( 1 ): 22 - 30 .
CHEN G L , WANG G W , HU J , et al . Survey on Chiplet packaging structure and communication structure [J ] . Journal of Computer Research and Development , 2022 , 59 ( 1 ): 22 - 30 . (in Chinese)
HUTNER M , SETHURAM R , VINNAKOTA B , et al . Special session: Test challenges in a Chiplet marketplace [C ] // 2020 IEEE 38th VLSI Test Symposium (VTS) . Piscataway : IEEE , 2020 : 1 - 12 .
DEHLAGHI B , WARY N , CARUSONE T C . Ultra-short-reach interconnects for die-to-die links: Global bandwidth demands in microcosm [J ] . IEEE Solid-State Circuits Magazine , 2019 , 11 ( 2 ): 42 - 53 .
李应选 . Chiplet的现状和需要解决的问题 [J ] . 微电子学与计算机 , 2022 , 39 ( 5 ): 1 - 9 .
LI Y X . The state-of-the-art of Chiplet and problems need be solved [J ] . Microelectronics & Computer , 2022 , 39 ( 5 ): 1 - 9 . (in Chinese)
钟伟军 , 任翔 , 赵鑫 . 异构集成芯片关键技术研究 [J ] . 信息技术与标准化 , 2021 ( 7 ): 6 - 10 .
ZHONG W J , REN X , ZHAO X . Research on key technologies of heterogeneous integrated chip [J ] . Information Technology & Standardization , 2021 ( 7 ): 6 - 10 . (in Chinese)
YOUSRY R , CHEN E , YING Y M , et al . 11.1 A 1.7pJ/b 112Gb/s XSR transceiver for intra-package communication in 7nm FinFET technology [C ] // 2021 IEEE International Solid-State Circuits Conference (ISSCC) . Piscataway : IEEE , 2021 : 180 - 182 .
SHIVNARAINE R , VAN IERSSEL M , FARZAN K , et al . 11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b efficiency in 7nm CMOS [C ] // 2021 IEEE International Solid-State Circuits Conference (ISSCC) . Piscataway : IEEE , 2021 : 181 - 183 .
GANGASANI G , HANSON D , STORASKA D , et al . A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS [C ] // 2022 IEEE International Solid-State Circuits Conference (ISSCC) . Piscataway : IEEE , 2022 : 122 - 124 .
俞武 . 数据中心下一代高速互联技术PAM4设计挑战与应对方案 [J ] . 中国集成电路 , 2021 , 30 ( 12 ): 26 - 30 .
YU W . Design challenges and solutions of PAM4, the next generation high-speed interconnection technology in data center [J ] . China Integrated Circuit , 2021 , 30 ( 12 ): 26 - 30 . (in Chinese)
SHIBASAKI T , DANJO T , OGATA Y , et al . 3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS [C ] // 2016 IEEE International Solid-State Circuits Conference (ISSCC) . Piscataway : IEEE , 2016 : 64 - 65 .
ERETT M , CAREY D , HUDNER J , et al . A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET [C ] // 2018 IEEE International Solid-State Circuits Conference - (ISSCC) . Piscataway : IEEE , 2018 : 274 - 276 .
倪芸 , 金鑫 , 姚晓东 . 基于EPON的SerDes差分信号完整性分析设计 [J ] . 光通信技术 , 2013 , 37 ( 9 ): 59 - 62 .
NI Y , JIN X , YAO X D . Signal integrity analysis of SerDes differential based on EPON system [J ] . Optical Communication Technology , 2013 , 37 ( 9 ): 59 - 62 . (in Chinese)
彭嘉豪 , 李儒章 , 付东兵 , 等 . 基于差分编码技术的12.5Gbp/s高速SerDes发射机设计 [J ] . 微电子学 , 2021 , 51 ( 1 ): 85 - 90 .
PENG J H , LI R Z , FU D B , et al . Design of 12.5Gbp/s high-speed SerDes transmitter based on differential encoding technology [J ] . Microelectronics , 2021 , 51 ( 1 ): 85 - 90 . (in Chinese)
WILSON J M , TURNER W J , POULTON J W , et al . A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator [C ] // 2018 IEEE International Solid-State Circuits Conference - (ISSCC) . Piscataway : IEEE , 2018 : 276 - 278 .
MCCOLLOUGH K , HUSS S D , VANDERSAND J , et al . 11.3 A 480Gb/s/mm 1.7pJ/b short-reach wireline transceiver using single-ended NRZ for die-to-die applications [C ] // 2021 IEEE International Solid-State Circuits Conference (ISSCC) . Piscataway : IEEE , 2021 : 1 - 3 .
UCIe . Specification revision 1.0 [EB/OL ] . ( 2022-02-24 )[ 2023-03-09 ] . https://www.uciexpress.org/specification https://www.uciexpress.org/specification .
SHOKROLLAHI A , CARNELLI D , FOX J , et al . 10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS [C ] // 2016 IEEE International Solid-State Circuits Conference (ISSCC) . Piscataway : IEEE , 2016 : 182 - 183 .
TAJALLI A , BASTANI PARIZI M , CARNELLI D A , et al . A 1.02-pJ/b 20.83-Gb/s/wire USR transceiver using CNRZ-5 in 16-nm FinFET [J ] . IEEE Journal of Solid-State Circuits , 2020 , 55 ( 4 ): 1108 - 1123 .
杨嘉伟 , 欧阳长月 . 沃尔什码分多路数字通信中的多电平压缩 [J ] . 电子学报 , 1990 , 18 ( 3 ): 122 - 124 .
YANG J W , OUYANG C Y . The multilevel compression in Walsh code-division multiplexing digital communication [J ] . Acta Electronica Sinica , 1990 , 18 ( 3 ): 122 - 124 . (in Chinese)
竺南直 , 张其善 . 广义沃尔什函数的构造与生成 [J ] . 电子学报 , 1992 , 20 ( 1 ): 81 - 84 .
ZHU N Z , ZHANG Q S . The construction and generation of generalized Walsh functions [J ] . Acta Electronica Sinica , 1992 , 20 ( 1 ): 81 - 84 . (in Chinese)
BERGANO N S , KERFOOT F W , DAVIDSION C R . Margin measurements in optical amplifier system [J ] . IEEE Photonics Technology Letters , 1993 , 5 ( 3 ): 304 - 306 .
CHEN S , LI H , CHIANG P Y . A robust energy/area-efficient forwarded-clock receiver with all-digital clock and data recovery in 28-nm CMOS for high-density interconnects [J ] . IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2016 , 24 ( 2 ): 578 - 586 .
CELIK F , AKKAYA A , TAJALLI A , et al . A 32-Gb/s PAM-4 SST transmitter with four-tap FFE using high-impedance driver in 28-nm FDSOI [J ] . IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2021 , 29 ( 6 ): 1132 - 1140 .
刘登宝 , 王子谦 , 白雪飞 , 等 . 基于SST驱动器的低功耗10 Gbit/s发射机 [J ] . 微电子学 , 2018 , 48 ( 3 ): 338 - 343 .
LIU D B , WANG Z Q , BAI X F , et al . A low power 10 Gbit/s transmitter based on SST driver [J ] . Microelectronics , 2018 , 48 ( 3 ): 338 - 343 . (in Chinese)
王娟会 , 张昌民 , 赵永瑞 . 有源电感的应用 [J ] . 电子科技 , 2010 , 23 ( 1 ): 56 - 58, 61 .
WANG J H , ZHANG C M , ZHAO Y R . The application of active inductor [J ] . Electronic Science and Technology , 2010 , 23 ( 1 ): 56 - 58, 61 . (in Chinese)
张明科 , 胡庆生 . 一个用于背板通信的24Gb/s高速自适应组合均衡器 [J ] . 电子学报 , 2017 , 45 ( 7 ): 1608 - 1612 .
ZHANG M K , HU Q S . A 24Gb/s high speed adaptive combined equalizer for backplane communication [J ] . Acta Electronica Sinica , 2017 , 45 ( 7 ): 1608 - 1612 . (in Chinese)
RAZAVI B . The active inductor[A circuit for all seasons] [J ] . IEEE Solid-State Circuits Magazine , 2020 , 12 ( 2 ): 7 - 11 .
LAI M C , ZHANG G , LV F X , et al . A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28nm CMOS [J ] . Microelectronics Journal , 2022 , 130 : 105628 .
郭凯乐 , 王和明 , 刘涛 , 等 . 基于高速SerDes中非等值尾电流源技术的新型高线性度相位插值器设计 [J ] . 空军工程大学学报(自然科学版) , 2020 , 21 ( 4 ): 61 - 67 .
GUO K L , WANG H M , LIU T , et al . A non-equivalent tail current source based new phase interpolator with high linearity for high-speed SerDes [J ] . Journal of Air Force Engineering University (Natural Science Edition) , 2020 , 21 ( 4 ): 61 - 67 . (in Chinese)
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