基于负电容电路的高速列总线读出方法

许睿明; 郭仲杰; 刘绥阳; 余宁梅

doi:10.12263/DZXB.20240948

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基于负电容电路的高速列总线读出方法

学术论文 | 更新时间：2025-07-24

- 基于负电容电路的高速列总线读出方法
- High-Speed Column Bus Readout Method Based on Negative Capacitance Circuit
- 电子学报 2025年53卷第4期页码：1192-1200
- 作者机构：
  
  西安理工大学自动化与信息工程学院，陕西西安 710048
- 作者简介：
  
  [ "许睿明男，1997年2月出生于内蒙古巴彦淖尔.现为西安理工大学自动化与信息工程学院硕士研究生.主要研究方向为超大规模集成电路设计.E-mail: rmxu@stu.xaut.edu.cn" ]
  [ "郭仲杰男，1982年1月出生于陕西韩城.现为西安理工大学自动化与信息工程学院教授.主要研究方向为超大规模数模混合集成电路的设计.E-mail: zjguo@xaut.edu.cn" ]
  [ "刘绥阳女，1997年8月出生于陕西咸阳.现为西安理工大学自动化与信息工程学院博士研究生.主要研究方向为超大规模数模混合集成电路的设计.E-mail: syliu@stu.xaut.edu.cn" ]
  [ "余宁梅女，1963年1月出生于广东梅州.现为西安理工大学自动化与信息工程学院教授.主要研究方向为大规模集成电路设计与工艺.E-mail: yunm@xaut.edu.cn" ]
- 基金信息：
  
  国家自然科学基金(62171367);陕西省创新能力支撑计划项目(2022TD-39)
- DOI：10.12263/DZXB.20240948
  中图分类号： TN47;
- 收稿：2024-10-17，
  
  修回：2025-04-17，
  
  纸质出版：2025-04-25
- 稿件说明：
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许睿明, 郭仲杰, 刘绥阳, 等. 基于负电容电路的高速列总线读出方法[J]. 电子学报, 2025, 53(04): 1192-1200.

XU Rui-ming, GUO Zhong-jie, LIU Sui-yang, et al. High-Speed Column Bus Readout Method Based on Negative Capacitance Circuit[J]. Acta Electronica Sinica, 2025, 53(04): 1192-1200.
许睿明, 郭仲杰, 刘绥阳, 等. 基于负电容电路的高速列总线读出方法[J]. 电子学报, 2025, 53(04): 1192-1200. DOI：10.12263/DZXB.20240948

XU Rui-ming, GUO Zhong-jie, LIU Sui-yang, et al. High-Speed Column Bus Readout Method Based on Negative Capacitance Circuit[J]. Acta Electronica Sinica, 2025, 53(04): 1192-1200. DOI：10.12263/DZXB.20240948

摘要

针对超大面阵CMOS图像传感器列总线建立时间过长的问题，本文提出了一种高速列总线信号读出方法.该方法基于负电容技术，将负电容电路集成到列级读出电路中，抵消列总线寄生电容对列总线信号建立时间的负面影响.同时，基于动态环路稳定性调节技术，平衡了读出速度与环路稳定性的设计矛盾.本文基于55 nm 1P4M CMOS工艺对提出的高速列总线读出方法完成了详细电路设计和全面仿真验证.在像素尺寸10 μm × 10 μm，尾电流为5 μA，列总线输出电压摆幅为1.2 V的设计条件下，列总线信号上升建立时间从1.721 μs减少至1.204 μs，降低了30.04%.列总线信号下降建立时间从5.780 μs降低至2.816 μs，降低了51.28%.此外，行固定模式噪声从1.30%降低到0.01%.在1.6 W的功耗下，本文设计的大面阵CMOS图像传感器的帧率和动态范围分别达到了27帧每秒和85 dB，为大面阵高速低功耗CMOS图像传感器的设计提供了一定的理论支撑.

Abstract

Aiming at the problem of the long establishment time of the column bus signal in large array CMOS image sensors

a high-speed column bus signal reading method is proposed in this paper. Based on negative capacitance technology

the negative capacitance circuit is integrated into the column-level readout circuit to offset the negative influence of column bus parasitic capacitance on the establishment time of column bus signal. At the same time

based on the dynamic loop stability regulation technology

the design contradiction between readout speed and loop stability is balanced. Based on 55 nm 1P4M CMOS technology

detailed circuit design and comprehensive simulation verification of the proposed high-speed column bus readout method are completed in this paper. Under the design conditions that the pixel size is 10 μm × 10 μm

the tail current is 5 μA

and the column bus output voltage swing is 1.2 V

the rise time of the column bus signal is reduced from 1.721 μs to 1.204 μs

which is reduced by 30.04%. The fall time of column bus signal is reduced by 51.28% from 5.780 μs to 2.816 μs. In addition

row fixed mode noise (RFPN) is reduced from 1.30% to 0.01%. Under the power consumption of 1.6 W

the frame rate and dynamic range of the large array CMOS image sensor designed in this paper reach 27 fps and 85 dB respectively. It provides a certain theoretical support for the design of large array high-speed and low-power CMOS image sensors.

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references

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