氧化物半导体薄膜晶体管的栅工程：材料、结构、界面与性能调控

谢雨农; 张志勇

doi:10.12263/DZXB.20250771

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氧化物半导体薄膜晶体管的栅工程：材料、结构、界面与性能调控

学术论文 | 更新时间：2026-04-24

- 氧化物半导体薄膜晶体管的栅工程：材料、结构、界面与性能调控
- Gate Engineering of Oxide Semiconductor Thin-Film Transistors: Materials, Structures, Interfaces, and Performance Modulation
- 电子学报 2025年53卷第12期页码：4541-4559
- 作者机构：
  
  1.中国计量大学计量测试与仪器学院，浙江杭州 310018
  2.北京大学电子学院纳米器件物理与化学教育部重点实验室碳基电子学研究中心，北京 100871
- 作者简介：
  
  [ "谢雨农女，1994年10月出生于浙江省温岭市.博士，就职于中国计量大学.主要研究方向为新型半导体材料单片三维集成技术.E-mail: rowenia@163.com" ]
  [ "张志勇男，1977年9月出生于湖北省应城市.博士，北京大学博雅特聘教授，博士生导师，纳米器件物理与化学教育部重点实验室主任，碳基电子学研究中心副主任.主要研究方向为碳基纳米电子学.E-mail: zyzhang@pku.edu.cn" ]
- 基金信息：
  
  国家自然科学基金(62401531)
- DOI：10.12263/DZXB.20250771
  中图分类号： TN4;TN6;TN7
- 收稿：2025-09-05，
  
  录用：2025-12-11，
  
  纸质出版：2025-12-25
- 稿件说明：
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谢雨农, 张志勇. 氧化物半导体薄膜晶体管的栅工程：材料、结构、界面与性能调控[J]. 电子学报, 2025, 53(12): 4541-4559.

XIE Yu-nong, ZHANG Zhi-yong. Gate Engineering of Oxide Semiconductor Thin-Film Transistors: Materials, Structures, Interfaces, and Performance Modulation[J]. Acta Electronica Sinica, 2025, 53(12): 4541-4559.
谢雨农, 张志勇. 氧化物半导体薄膜晶体管的栅工程：材料、结构、界面与性能调控[J]. 电子学报, 2025, 53(12): 4541-4559. DOI：10.12263/DZXB.20250771

XIE Yu-nong, ZHANG Zhi-yong. Gate Engineering of Oxide Semiconductor Thin-Film Transistors: Materials, Structures, Interfaces, and Performance Modulation[J]. Acta Electronica Sinica, 2025, 53(12): 4541-4559. DOI：10.12263/DZXB.20250771

摘要

氧化物半导体（Oxide Semiconductor，OS），特别是非晶氧化物半导体（Amorphous Oxide Semicondutor，AOS），因其适中的迁移率、极低的关态电流、优异的大面积均匀性以及与传统互补金属氧化物半导体（Complementary Metal Oxide Semiconductor，CMOS）工艺兼容的低温制备工艺，已成为突破硅基器件尺寸微缩物理极限的重要候选材料.近年来，AOS不仅在高端液晶显示（Liquid Crystal Display，LCD）与有机发光二极管（Organic Light-Emitting Diode，OLED）显示背板中实现了规模化应用，还在低功耗逻辑器件、高密度存储以及单片三维集成电路（Monolithic Three-Dimensional，M3D）等先进集成架构中展现出广阔的应用前景.尤其在M3D技术所要求的低热预算（

400 ℃）制造条件下，氧化物半导体在功耗、性能、面积与成本（Power-Performance-Area-Cost，PPAC）综合优化方面具备显著优势.在器件尺寸持续微缩的背景下，如何维持对沟道载流子的有效静电控制、抑制短沟道效应并保障器件长期可靠性，已成为制约氧化物半导体薄膜晶体管（Thin Film Transistors，TFTs）进一步发展的核心问题.其中，栅工程作为决定晶体管电学性能的关键环节，直接影响器件的阈值电压、亚阈值摆幅、漏电流以及偏置稳定性等重要指标.本文围绕氧化物半导体TFT的栅工程展开系统综述，重点从栅介质材料、栅结构设计以及栅-沟道界面工程三个方面总结近年来的研究进展与技术趋势.在栅介质层面，通过引入高介电常数（high-

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）材料及其复合结构，可在降低等效氧化层厚度的同时增强栅控能力、降低工作电压并有效抑制栅漏电流；在栅结构层面，采用鳍式晶体管、纳米线及全环绕栅（Gate-All-Aroud，GAA）等三维非平面结构，能够显著增强栅极对沟道的包裹性，从而缓解短沟道效应并提升器件在极限尺寸下的性能；在界面工程方面，通过界面钝化、能带调控及缺陷态调节等策略，可有效降低界面态密度，改善载流子输运特性，并显著提升器件的稳定性与可靠性.尽管氧化物半导体栅工程已取得显著进展，但仍面临若干关键挑战，包括器件可靠性机制的复杂性、现有界面优化策略在短沟道器件中的适用性，以及缺乏与n型氧化物半导体性能匹配且兼容后端工艺（Back End Of Line，BEOL）的高性能p型氧化物半导体材料.这些问题在一定程度上限制了互补电路及高密度集成应用的发展.总体而言，氧化物半导体作为后摩尔时代的重要技术路线，其发展潜力已得到学术界与产业界的广泛认可.随着栅工程相关材料、结构与界面调控技术的持续突破，氧化物半导体有望在未来高性能、低功耗电子器件与三维集成系统中发挥更加关键的作用.

Abstract

Oxide semiconductors (OS)

particularly amorphous oxide semiconductors (AOS)

have emerged as important candidates for overcoming the physical scaling limits of si

licon-based devices

owing to their moderate carrier mobility

extremely low off-state current

excellent large-area uniformity

and low-temperature fabrication processes compatible with conventional complementary metal-oxide-semiconductor (CMOS) technology. In recent years

AOS have not only achieved large-scale commercial applications in high-end liquid crystal display (LCD) and organic light-emitting diode (OLED) display backplanes

but have also demonstrated great potential in low-power logic devices

high-density memory

and advanced integration architectures such as monolithic three-dimensional integrated circuits (M3D). In particular

under the stringent low thermal budget (

400 °C) required for M3D fabrication

oxide semiconductors exhibit significant advantages in the comprehensive optimization of power

performance

area

and cost (PPAC).As device dimensions continue to scale down

maintaining effective electrostatic control over channel carriers

suppressing short-channel effects

and ensuring long-term device reliability have become critical challenges limiting the further development of oxide semiconductor thin-film transistors (TFTs). Among various design strategies

gate engineering plays a pivotal role in determining transistor electrical characteristics

directly affecting key performance metrics such as threshold voltage

subthreshold swing

leakage current

and bias stability. This paper presents a systematic review of gate engineering in oxide semiconductor TFTs

with a focus on recent advances and technological trends in gate dielectric materials

gate structure design

and gate-channel interface engineering. At the gate dielectric level

the introduction of high-permittivity (high-

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) materials and their composite structures enables enhanced gate controllability

reduced operating voltage

and effective suppression of gate leakage current by scaling down the equivalent oxide thickness. At the gate structure level

three-dimensional non-planar architectures—including FinFETs

nanowire transistors

and gate-all-around (GAA) structures—significantly improve gate-to-channel coupling

thereby alleviating short-channel effects and enhancing device performance at aggressive scaling limits. At the interface engineering level

strategies such as interface passivation

band alignment optimization

and defect state modulation effectively reduce interface trap density

improve carrier transport properties

and markedly enhance device stability and reliability.Despite the substantial progress achieved in gate engineering of oxide semiconductor devices

several critical challenges remain

including the complexity of reliability degradation mechanisms

the applicability of existing interface optimization strategies to short-channel devices

and the lack of high-performance p-type oxide semiconductor materials that are both compatible with back-end-of-line (BEOL) processes and performance-matched to n-type oxide semiconductors. These limitations hinder the development of complementary circuits and high-density integrated systems. Overall

oxide semiconductors are widely recognized as a key technological pathway in the post-Moore era

and with continued breakthroughs in gate-related materials

device structures

and interface control technologies

they are expected to play an increasingly important role in future high-performance

low-power electronic devices and three-dimensional integrated systems.

关键词

Keywords

references

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