JIANG Xiao-bo, YE De-sheng, WU Wen-tao, et al. Low Power Design of Asynchronous Datapath for LDPC Decoder[J]. Acta Electronica Sinica, 2013, 41(4): 685-689.
JIANG Xiao-bo, YE De-sheng, WU Wen-tao, et al. Low Power Design of Asynchronous Datapath for LDPC Decoder[J]. Acta Electronica Sinica, 2013, 41(4): 685-689. DOI: 10.3969/j.issn.0372-2112.2013.04.010.
Asynchronous datapath of LDPC decoder is proposed in this paper.Glitches and redundant computations are decreased by asynchronous design.Clock tree is replaced by handshake control units.Taking advantages of input data statistical characteristic
key arithmetic elements in the datapath are proposed.Two types of datapaths including synchronous design and clock-gating design are also implemented as contrasts.Three designs exploit similar architecture and realize the same function by 0.18μm CMOS process.Simulation result shows that the proposed asynchronous design features the lowest power.Compared with the synchronous and clock-gating designs
it saves 42.0% and 32.6% power respectively.Its performance is a little bit worse than the synchronous design
but is better than the clock-gating design.The delay of the synchronous design is 1.09ns