Ternary reversible logic synthesis is the extension and expansion of reversible logic synthesis.In order to simplify the reversible network and improve the generality of ternary reversible logic gate

the effective value of controlling bits of the existing ternary reversible controlled gates can be extended to any of 0

1 and 2.And on the basis of that

a ternary reversible logic synthesis algorithm with minimum chaos degree is proposed.The algorithm is used to compute the relative chaos degree and absolute chaos degree of each variable in truth table under ternary logic system

according to the reversible function.As one reversible logic gate is selected

the principle of minimal chaos degree

in ternary reversible logic synthesis should be followed until the relative chaos degree and absolute chaos degree of each variable in truth table decrease to 0

which means the synthesis has been finished

and the reversible network can be derived.The time complexity for the algorithm is

O

(

n

2

3

n

)

and its space complexity is

O

(

n

3

n

).The experimental results show that the average number of gates is less than the existing algorithms as known.