With the development of the integrated circuit(IC) manufacturing technology

very large scale integrated(VLSI) circuits test is faced with the problems of over large test data volume and high test power consumption.This paper presents a low-power multistage test data compression scheme to address these two problems.Firstly

the proposed scheme preprocesses the original test set with the input reduction technology so as to reduce the volume of specified bits;secondly

the scheme compresses test patterns shifted in multi-scan chains according to their compatibilities and uses shorter code to demonstrate compatible test patterns

namely the first stage of compression;thirdly

the low power X-filling is conducted:X-filling for capture power reduction is first conducted for the unspecified bits to keep the capture power under the given threshold and then the remaining unspecified bits are filled for shift power reduction;finally

the proposed scheme further compresses test patterns using modified run-length coding.Experimental results for ISCAS89 benchmark circuits demonstrate that

compared with golomb

FDR

EFDR

9C

BM code

etc.

the proposed scheme achieves better compression rate while reducing both the capture power and the shift power.