This paper introduces the design and implementation of equalizer in the backplane communication system.The equalizer uses a combination of continuous time linear equalizer (CTLE) and 2 tap decision feedback equalizer (DFE) to cancel both pre-cursor and post-cursors ISI.In the design

CTLE compensates with different frequencies of the loss of the channel by employing split-path equalizer

reduced the circuit area and power consumption.A half-rate speculative architecture is adopted to improve the transmitted data rate in DFE by relaxing the timing constraint on the first feedback path.An

analog implementation of the LMS algorithm is used to control the DFE tap coefficients.Circuit using IBM 0.13 m BiCMOS process design and implement.Measured results show that the eye is completely closed when 24Gb/s signal through 18 inches backplane

the horizontal opening degree of equalized eye reached 0.81UI.The entire equalizer chip area including pads is 0.780.8mm

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and consumes 624mW with the supply voltage of 3.3V.