ZHAO Yuan-fu, WANG Liang, YUE Su-ge, et al. Single Event Effect and its Hardening Technique in Nano-scale CMOS Integrated Circuits[J]. Acta Electronica Sinica, 2018, 46(10): 2511-2518.
ZHAO Yuan-fu, WANG Liang, YUE Su-ge, et al. Single Event Effect and its Hardening Technique in Nano-scale CMOS Integrated Circuits[J]. Acta Electronica Sinica, 2018, 46(10): 2511-2518. DOI: 10.3969/j.issn.0372-2112.2018.10.027.
The integrated circuits used in aerospace can be influenced by space radiation effects
leading to some problems such as transient disturbance
data upset
performance degradation
functional failure or even destructive damage. The variety and complexity of these problems increases as the feature size of devices scales down to less than 100 nm (called as "nano-scale" in this paper). Single event effect has become a main reliability factor for space-used ICs
and brought about much challenge to radiation hardness assurance and radiation hardening. Taking nano-scale ICs as the research object
combined with recent technology progress
this paper introduces the research achievements in single event effect and hardening techniques of 65 nm ICs
including the proposed time-domain testing and analyzing method
radiation hardening techniques for single event multi-node upsets and single event transients.