The existing real-world or simulated fault injection methods cannot meet the requirements of reliability verification of nanoscale microprocessors for space applications

since they may introduce problems such as high cost

poor flexibility

poor observability

and low accuracy. This paper proposes a hardware/software cooperated fault injection scheme based on backplane

the time and positions of fault are generated in software

and injected into hardware design at register transfer level. Further

a multi-bit fault model focuses on radiation-induced soft error is proposed for register and memory. Experimental results show that the proposed software and hardware co-designed fault injection platform provides a high automation

randomicity and non-intrusion reliability evaluation method for fault-tolerant processor design.