沈阳工业大学信息科学与工程学院,辽宁,沈阳,110870
网络出版:2019-09-25,
纸质出版:2019
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常丽, 朱宇祥, 蒋辉. 量子全加器设计[J]. 电子学报, 2019,47(9):1863-1867.
CHANG Li, ZHU Yu-xiang, JIANG Hui. Design of Quantum Full Adder[J]. Acta Electronica Sinica, 2019, 47(9): 1863-1867.
常丽, 朱宇祥, 蒋辉. 量子全加器设计[J]. 电子学报, 2019,47(9):1863-1867. DOI: 10.3969/j.issn.0372-2112.2019.09.007.
CHANG Li, ZHU Yu-xiang, JIANG Hui. Design of Quantum Full Adder[J]. Acta Electronica Sinica, 2019, 47(9): 1863-1867. DOI: 10.3969/j.issn.0372-2112.2019.09.007.
量子全加器是量子计算机的基本单元,为了减少能耗,降低构造成本及物理实现难度,本文提出一种新型
n
位量子全加器,使用3
n
个CNOT(Controlled NOT)门和2
n
-1个Toffoli门实现
n
位量子加减法,采用超前进位方式,不含进位输入,通过最高溢出标志位判断加法的进位和减法的正负号,标志位不参与高低位计算,不增加电路延时,适合
n
位量子并行计算.随机生成4、8、16和32位数分别进行加减仿真操作,验证了全加器的正确性.该全加器量子代价较低,结构简单,有利于提高集成电路规模和集成度.
Quantum full adder is the basic elements of quantum computers
in order to reduce the energy loss and cut the construction cost and the difficulty of physical realization. The paper proposes a new type of
n
-bit quantum full adder which uses 3
n
CNOT(Controlled NOT) Gates and 2
n
-1 Toffoli gates to implement
n
-bit quantum addition and subtraction
adopts the carry look-ahead mode without carry input
and judges the carry of addition and positive and negative sign of subtraction with the highest overflow mark bit that does not participate in the calculation of high and low bit
which does not increase time delay of the circuit and suits for
n
-bit quantum parallel operation. The simulation operation with random number of 4
8
16 and 32 di
gits verifies the correctness of the full adder separately. The low quantum cost and simple circuit structure of the quantum full adder is helpful to improve the size and integration of integrated circuits.
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