Abstract:The integrated circuits used in aerospace can be influenced by space radiation effects,leading to some problems such as transient disturbance,data upset,performance degradation,functional failure or even destructive damage.The variety and complexity of these problems increases as the feature size of devices scales down to less than 100 nm (called as "nano-scale" in this paper).Single event effect has become a main reliability factor for space-used ICs,and brought about much challenge to radiation hardness assurance and radiation hardening.Taking nano-scale ICs as the research object,combined with recent technology progress,this paper introduces the research achievements in single event effect and hardening techniques of 65 nm ICs,including the proposed time-domain testing and analyzing method,radiation hardening techniques for single event multi-node upsets and single event transients.
赵元富, 王亮, 岳素格, 孙永姝, 王丹, 刘琳, 刘家齐, 王汉宁. 纳米级CMOS集成电路的单粒子效应及其加固技术[J]. 电子学报, 2018, 46(10): 2511-2518.
ZHAO Yuan-fu, WANG Liang, YUE Su-ge, SUN Yong-shu, WANG Dan, LIU Lin, LIU Jia-qi, WANG Han-ning. Single Event Effect and its Hardening Technique in Nano-scale CMOS Integrated Circuits. Acta Electronica Sinica, 2018, 46(10): 2511-2518.
[1] Robert Ecoffet.On-Orbit Anomalies:Investigations and Root Cause Determination[M].Las Vegas:IEEE NSREC Short Course,2011.
[2] G E Moore.Cramming more components onto integrated circuits[J].Electronics,1965,38(8):114~117.
[3] Suge Yue,et al.Modeling and simulation of single-event effect in CMOS circuit[J].Journal of Semiconductors,2015,36(11):111002-1-10.
[4] C Inguimbert,et al.Electron induced SEUs:Micro-dosimetry in nano-metric volumes[J].IEEE Trans Nucl Sci,2015,62(6):2846-2852.
[5] Robert Baumann.Single-Event Effects in Advanced CMOS Technology[M].Seattle:IEEE NSREC Short Course,2005.
[6] Kenneth P Rodbell,et al.Low-energy proton-induced single-event upsets in 65 nm node,silicon-on-insulator,latches and memory cells[J].IEEE Trans Nucl Sci,2007,54(6):2474-2479.
[7] M P King,et al.Electron-induced single event upsets in static random access memory[J].IEEE Trans Nucl Sci,2013,60(6):4122-4129.
[8] Matthew J Gadlage,et al.Electron-induced single-event upsets in 45-nm and 28-nm Bulk CMOS SRAM-Based FPGAs operating at nominal voltage[J].IEEE Trans Nucl Sci,2015,62(6):2717-2724.
[9] Philippe Roche,et al.SEE and TID Radiation Test Results of Digital Circuits Designed and Manufactured in ST 40nm/45nm/65nm/90nm/130nm CMOS Technologies[R].Crolles:European Space Agency,2011.
[10] David L Hansen,et al.Clock,flip-flop,and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology[J].IEEE Trans Nucl Sci,2009,56(6):3542-3550.
[11] 罗尹红,等.纳米静态随机存储器低能质子单粒子翻转敏感性研究[J].物理学报,2016,65(6):068501-1-068501-10. Luo Yin-Hong et al.Single event upsets sensitivity of low energy proton in nanometer static random access memory[J].Acta Physica Sinica,2016,65(6):068501-1-10.(in Chinese)
[12] Oluwole A Amusan,et al.Charge clloction and charge sharing in a 130 nm CMOS technology[J].IEEE Trans Nucl Sci,2006,53(6):3253-3258.
[13] Lin Liu,et al.3D Simulation of charge collection and MNU in SEU hardened storage cells[A].2009 RADECS Proceeding[C].Bruges:RADECS,2009.230-234.
[14] S E Diehl,et al.Considerations for single event immune VLSI logic[J].IEEE Trans Nucl Sci,1983,30(6):4501-4507.
[15] Arthur L F,et al.Single event upset in combinatorial and sequential current mode logic[J].IEEE Trans Nucl Sci,1985,32(6):4216-4218.
[16] Matthew J Gadlage,et al.Increased single-event transient pulsewidths in a 90-nm bulk CMOS technology operating at elevated temperatures[J].IEEE Trans Device Mater Rel,2010,10(1):157-163.
[17] Jonathan R Ahlbin,et al.Single-event transient pulse quenching in advanced CMOS logic circuits[J].IEEE Trans Nucl Sci,2009,56(6):3050-3056.
[18] Suge Yue,et al.Single event transient pulse width measurement of 65nm bulk CMOS circuits[J].Journal of Semiconductors,2015,36(11):115006-1-4.
[19] Lin Liu,et al.The 65nm double-DICE storage element based on error-quenching layout design to reduce single-event multiple node upsets[A].2016 RADECS Proceeding[C].Bremen:RADECS,2016.1-6.
[20] Yuanfu Zhao,et al,SEU and SET of 65nm bulk CMOS flip-flops and their implications for RHBD[J].IEEE Trans Nucl Sci,2015,62(6):2666-2672.
[21] Xinyuan Zhao,et al.Single event transients of scan flip-flop and an SET-immune redundant delay filter (RDF)[A].RADECS,2013[A].2013 RADECS Proceeding[C].Oxford:RADECS,2013.1-5.