一种具有自适应优化电源抑制比的低静态电流无片外电容LDO

doi:10.12263/DZXB.20201137

电子学报 ›› 2022, Vol. 50 ›› Issue (7): 1674-1683.DOI: 10.12263/DZXB.20201137

一种具有自适应优化电源抑制比的低静态电流无片外电容LDO

徐叶¹, 张培勇¹, 李豪¹, 黄开天²

^1.浙江大学超大规模集成电路研究所，浙江杭州 310027
^2.南方电网科学研究院有限责任公司信息安全中心，广东广州 510663

收稿日期:2020-10-14 修回日期:2021-02-19 出版日期:2022-07-25
- 作者简介:
- 徐叶女，1995年生，浙江江山人.浙江大学信息与电子工程学院硕士研究生.主要研究方向为模拟集成电路.E-mail: yeahz@zju.edu.cn
  张培勇（通讯作者）男，1977年生，安徽安庆人.浙江大学获博士.主要研究方向为超大规模集成电路设计.E-mail: zhangpy@zju.edu.cn
  李豪男，1995年生，浙江嘉兴人.浙江大学信息与电子工程学院博士研究生.主要研究方向为SoC电路设计.E-mail: 11931078@zju.edu.cn
  黄开天男，1992年生，广西钦州人.清华大学硕士.主要研究方向为电力物联网通信与传感器应用安全、密码芯片应用.E-mail: huangkt@csg.cn
- 基金资助:
- 国家重点研发计划 (2018YFB0904900)

A Low-Quiescent-Current Capacitor-less LDO Using an Adaptive PSR Optimization Technique

XU Ye¹, ZHANG Pei-yong¹, LI Hao¹, HUANG Kai-tian²

^1.The Institute of VLSI Design, Zhejiang University, Hangzhou, Zhejiang 310027, China
^2.Information Security Center, China Southern Power Grid Research Institute Co., Ltd., Guangzhou, Guangdong 510663, China

Received:2020-10-14 Revised:2021-02-19 Online:2022-07-25 Published:2022-07-30
- Supported by:
- National Key Research and Development Program of China (2018YFB0904900)

摘要/Abstract

摘要：

为改善无片外电容LDO（Capacitor-Less Low-DropOut regulator，CL-LDO）的电源抑制比（Power Supply Rejection，PSR），本文提出一种低静态电流PSR自适应优化方案.采用push-pull放大器，避免复杂的频率补偿电路与片外大电容，缩小了面积.为优化中频段PSR，在功率管栅极注入一个与频率相关的补偿电流.采用低静态电流的补偿电流动态调整方案，减小压差和负载电流变化对PSR优化效果的影响.该LDO基于0.11 μm CMOS工艺，芯片面积为0.026 mm².测试结果表明，在0.1~80 mA负载电流下，静态电流最大值为55 $μ$ A.在8 kHz到1 MHz频率范围内，在不同压差和负载电流下，PSR最大优化值为21~37 dB.

关键词: 无片外电容低压差线性稳压器, 电源抑制比, 可适应电源噪声消除, 低静态电流, 频率补偿

Abstract:

To improve the power supply rejection ratio(PSR) of capacitor-less low dropout regulator(CL-LDO), this paper proposes an adaptive optimization technique for PSR with low quiescent current. Using push-pull amplifier avoids complex frequency compensation circuits and a bulky external capacitor, thereby reducing the area. To optimize the mid-band PSR, a frequency-dependent compensation current is injected into the gate of the pass transistor. Moreover, a low power dynamic adjustment scheme of the compensation current is adopted to alleviate the impacts of the dropout voltage and load current variations on the optimal PSR improvement. This LDO was designed and fabricated in a 0.11 μm CMOS technology with an active area of 0.026 mm². The experimental results show that the maximum quiescent current is 55 μA with 0.1-80 mA load current. In the frequency range of 8 kHz to 1 MHz, the maximum PSR improvement is 21-37 dB with different dropout voltages and load currents.

Key words: capacitor-less low-dropout regulator, power supply rejection ratio, adaptive supply-ripple cancellation, low quiescent current, frequency compensation

中图分类号:

TN431.1

徐叶, 张培勇, 李豪, 黄开天. 一种具有自适应优化电源抑制比的低静态电流无片外电容LDO[J]. 电子学报, 2022, 50(7): 1674-1683.

XU Ye, ZHANG Pei-yong, LI Hao, HUANG Kai-tian. A Low-Quiescent-Current Capacitor-less LDO Using an Adaptive PSR Optimization Technique[J]. Acta Electronica Sinica, 2022, 50(7): 1674-1683.

图/表 22

图1 电源-输出噪声耦合路径图

图2 LDO小信号等价模型

图3 Mpass的Cgd,Vdsat,Vds,Vgs与Ccomp随负载电流变化曲线图(Vdrop=200 mV,Vth=-640 mV)

图4 Mpass在不同Vdrop下,Ccomp随负载电流变化曲线图

图5 LDO主模块原理图

表1 push-pull放大器MOS管比例表

MOS管	比例
M_AH2:M_HL1:M_HL2:M_AL2:M_AL1:M_AH1	2:2:2:2:1:1
M_HL3:M_HL4 & M_AP2:M_AP1	1:1
M_AH3:M_AH4:M_AH5:M_AN2	1:1:1:1
M_AL3:M_AL4:M_AL5:M_AN1	1 $∶$ 1:1:1

表1 push-pull放大器MOS管比例表

MOS管	比例
M_AH2:M_HL1:M_HL2:M_AL2:M_AL1:M_AH1	2:2:2:2:1:1
M_HL3:M_HL4 & M_AP2:M_AP1	1:1
M_AH3:M_AH4:M_AH5:M_AN2	1:1:1:1
M_AL3:M_AL4:M_AL5:M_AN1	1 $∶$ 1:1:1

图6 LDO主模块开环交流响应图(Cload=100 pF)

图7 电流放大电路Stage1原理图

图8 电流放大电路Stage2原理图

图9 PSR跨导增益增强电路开环交流响应图

图10 电流放大电路交流仿真图(Cvar=300 fF)

图11 PSR动态调节电路原理图

表2 PSR动态调节电路部分MOS管比例表

MOS管	比例	K_MD_i
M_DN2: M_DN3_i	1:1
M_DP31: M_DP2	1:2	$0.5$
M_DP32: M_DP2	1:1	1
M_DP33: M_DP2	2:1	$2$
M_DP34: M_DP2	3:1	$3$

表2 PSR动态调节电路部分MOS管比例表

MOS管	比例	K_MD_i
M_DN2: M_DN3_i	1:1
M_DP31: M_DP2	1:2	$0.5$
M_DP32: M_DP2	1:1	1
M_DP33: M_DP2	2:1	$2$
M_DP34: M_DP2	3:1	$3$

图12 Ccomp,VG,P和f(KMDi )随负载电流变化曲线图(VIN=2 V,VOUT=1.8 V)

表3 MDP5i 寄生电容值表

MOS管	MOS电容/fF
M_DN50	50
M_DN51	10
M_DN52	40
M_DN53	80
M_DN54	100

图13 瞬态响应优化模块原理图

图14 CL-LDO芯片封装照片

图15 LDO测试设置

图16 CL-LDO在不同压差下静态电流随负载电流变化的曲线

图17 CL-LDO有无PSR Enhancer的PSR测试对比图(Cload=100 pF)

图18 CL-LDO 瞬态响应(Cload=100 pF) 图

表4 CL-LDO主要性能比较表

参数		本文		TCAS-II ^[11]	JSSC ^[12]	JSSC ^[13]
工艺		CMOS 0.11 μm		CMOS 0.18 μm	CMOS 65 nm	CMOS 0.18 μm
主极点位置		功率管栅极		功率管栅极	功率管栅极	功率管栅极
输出电压/V/压差/V		1.8 / 0.2		1.6 / 0.2	1 / 0.2	1.6 / 0.2
静态电流/μA		45.5~55		71~101	8~297.5	55~555
可负载电容/pF		0~100		0~100	0~240	0~100
可负载电流/mA		0.1~80		0.2~100	1~25	0~50
面积/mm²		0.026*		0.033*	0.087**	0.14*
PSR优化技术		自适应前馈补偿电流		NCC(非自适应)	ASRC	自适应寄生电容前馈补偿电流
PSR		优化前@60 mA	优化后@60 mA	-50 @100 kHz	-65 @10 kHz -58 @100 kHz	-52 @10 kHz -51 @100 kHz
PSR		-26 @10 kHz -16 @100 kHz	-40.6 @10 kHz -35 @100 kHz	-50 @100 kHz	-65 @10 kHz -58 @100 kHz	-52 @10 kHz -51 @100 kHz
负载瞬态响应	过冲/下冲电压/mV	200/245		210 / -	153 / 225	120 / 80
负载瞬态响应	恢复时间/ $μ$ s/负载电流阶跃时间/ $μ$ s	3/0.5		0.2 / 0.1	1.3 /0.1	<6 / 0.1
FOM***/mV		0.842		0.11	2.789	1.332

表4 CL-LDO主要性能比较表

参数		本文		TCAS-II ^[11]	JSSC ^[12]	JSSC ^[13]
工艺		CMOS 0.11 μm		CMOS 0.18 μm	CMOS 65 nm	CMOS 0.18 μm
主极点位置		功率管栅极		功率管栅极	功率管栅极	功率管栅极
输出电压/V/压差/V		1.8 / 0.2		1.6 / 0.2	1 / 0.2	1.6 / 0.2
静态电流/μA		45.5~55		71~101	8~297.5	55~555
可负载电容/pF		0~100		0~100	0~240	0~100
可负载电流/mA		0.1~80		0.2~100	1~25	0~50
面积/mm²		0.026*		0.033*	0.087**	0.14*
PSR优化技术		自适应前馈补偿电流		NCC(非自适应)	ASRC	自适应寄生电容前馈补偿电流
PSR		优化前@60 mA	优化后@60 mA	-50 @100 kHz	-65 @10 kHz -58 @100 kHz	-52 @10 kHz -51 @100 kHz
PSR		-26 @10 kHz -16 @100 kHz	-40.6 @10 kHz -35 @100 kHz	-50 @100 kHz	-65 @10 kHz -58 @100 kHz	-52 @10 kHz -51 @100 kHz
负载瞬态响应	过冲/下冲电压/mV	200/245		210 / -	153 / 225	120 / 80
负载瞬态响应	恢复时间/ $μ$ s/负载电流阶跃时间/ $μ$ s	3/0.5		0.2 / 0.1	1.3 /0.1	<6 / 0.1
FOM***/mV		0.842		0.11	2.789	1.332

参考文献 21

1	HINOJOJ M, MARTÍNEZCL, TORRALBAA. Internally Compensated LDO Regulators for Modern System-on-Chip Design[M]. Switzerland: Springer, 2018: 14-28.
2	CHEN, KE-HORNG. Power Management Techniques for Integrated Circuit Design[M]. Singapore: John Wiley & Sons Singapore Pte. Ltd., 2016: 34-49.
3	GUPTAV, RINCÓN-MORAG. A low dropout, CMOS regulator with high PSR over wideband frequencies[C]//2005 IEEE International Symposium on Circuits and Systems. Japan: IEEE, 2005: 4245-4248.
4	LEEC H, MCCLELLANK, CHOMAJ. A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter[J]. IEEE Journal of Solid-State Circuits, 2001, 36(10): 1453-1463.
5	INGINOJ M, KAENELV V. A 4-GHz clock system for a high-performance system-on-a-chip design[J]. IEEE Journal of Solid-State Circuits, 2001, 36(11): 1693-1698.
6	YANGB, DROSTB, RAOS, et al. A high-PSR LDO using a feedforward supply-noise cancellation technique[C]//2011 IEEE Custom Integrated Circuits Conference(CICC). USA: IEEE, 2011: 1-4.
7	EL-NOZAHIM, AMERA, TORRESJ, et al. High PSR low drop-out regulator with feed-forward ripple cancellation technique[J]. IEEE Journal of Solid State Circuits, 2010, 45(3): 565-577.
8	HoE N Y. Wide-loading-range fully integrated LDR with a power-supply ripple injection filter[J]. IEEE Transactions on Circuits & Systems II Express Briefs, 2012, 59(6): 356-360.
9	JIANGJ Z, WEIS, JOSEPHS, et al. A 65-nm CMOS low dropout regulator featuring > 60-dB PSRR over 10-MHz frequency range and 100-mA load current range[J]. IEEE Journal of Solid-State Circuits, 2018, 53(8): 2331-2342.
10	JOSHIK, MANANDHARS, BAKKALOGLUB. A 5.6 μA wide bandwidth, high power supply rejection linear low-dropout regulator with 68 dB of PSR up to 2 MHz[J]. IEEE Journal of Solid-State Circuits, 2020, 55(8): 2151-2160.
11	YUNS J, YUNJ S, YONGS K. Capless LDO regulator achieving -76 dB PSR and 96.3 fs FOM[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2016, 64(10): 1147-1151.
12	LIM Y, LEEJ, PARKS, et al. An external capacitorless low-dropout regulator with high PSR at all frequencies from 10 kHz to 1 GHz using an adaptive supply-ripple cancellation technique[J]. IEEE Journal of Solid-State Circuits, 2018, 53(9): 2675-2685.
13	CHANG-JOONP, ONABAJOM, SILVA-MARTINEZJ. External capacitor-less low drop-out regulator with 25 dB superior power supply rejection in the 0.4—4 MHz range[J]. IEEE Journal of Solid-State Circuits, 2013, 49(2): 486-501.
14	MANT Y, MOKP K T, CHANM. A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement[J]. IEEE Transactions on Circuits & Systems II Express Briefs, 2007, 54(9): 755-759.
15	LIG, QIANH, GUOJ, et al. Dual active-feedback frequency compensation for output-capacitorless LDO with transient and stability enhancement in 65-nm CMOS.[J] IEEE Transactions on Power Electronics, 2019, 35(1): 415-429.
16	MINGX, LIQ, ZHOUZ K, et al. An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control[J]. Circuits and Systems II: Express Briefs, IEEE Transactions on, 2012, 59(1): 40-44.
17	CHAVA CHAITANYAK, JOSESILVA-MARTINEZ. A frequency compensation scheme for LDO voltage regulators[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2004, 51(6): 1041-1050.
18	LINH C, WUH H, CHANGT Y. An active-frequency compensation scheme for cmos low-dropout regulators with transient-response improvement[J]. IEEE Transactions on Circuits & Systems II Express Briefs, 2008, 55(9): 853-857.
19	QUX, ZHOUZ K, ZHANGB, et al. An ultralow-power fast-transient capacitor-free low-dropout regulator with assistant push-pull output stage[J]. IEEE Transactions on Circuits & Systems II Express Briefs, 2013, 60(2): 96-100.
20	HUANGY, LUY, MALOBERTIF, et al. Nano-ampere low-dropout regulator designs for iot devices[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(11): 4017-4026.
21	GUOJ, LEUNGK N. A 6-w chip-area-efficient output-capacitorless ldo in 90-nm CMOS technology[J]. IEEE Journal of Solid State Circuits, 2010, 45(9): 1896-1905.

[1]	李俊宏;李平;张国俊;翟亚红;许剑波. 一种双极工艺下抗辐照PWM推挽转换电路的研究[J]. 电子学报, 2011, 39(11): 2492-2496.
[2]	高文焕;李冬梅. 一种高速宽带BJT模拟开关的设计与实现[J]. 电子学报, 2000, 28(11): 122-124.

一种具有自适应优化电源抑制比的低静态电流无片外电容LDO

A Low-Quiescent-Current Capacitor-less LDO Using an Adaptive PSR Optimization Technique

RichHTML

PDF

可视化

摘要/Abstract

引用本文

使用本文

图/表 22

参考文献 21

相关文章 2

编辑推荐

Metrics