AIS多小区同频信号实时盲分离的FPGA设计

doi:10.3969/j.issn.0372-2112.2017.09.010

电子学报 ›› 2017, Vol. 45 ›› Issue (9): 2121-2126.DOI: 10.3969/j.issn.0372-2112.2017.09.010

AIS多小区同频信号实时盲分离的FPGA设计

唐然^1,2, 吴虹^1,2, 赵迎新^1,2, 穆巍炜^1,2, 徐锡燕^1,2, 马肖旭^1,2, 刘兵^1,2, 刘之洋^1,2

1. 南开大学电子信息与光学工程学院, 天津 300350;
2. 天津市光电传感器与传感网络技术重点实验室, 天津 300350

收稿日期:2016-01-27 修回日期:2016-05-11 出版日期:2017-09-25
- 通讯作者:
- 赵迎新
- 作者简介:
- 唐然,男,1991年生于安徽巢湖.现为南开大学电子信息与光学工程学院博士研究生.主要研究方向为盲信号处理,信号处理算法的FPGA实现.E-mail:913230983@qq.com;吴虹,女,1967年生于天津.现为南开大学教授、博士生导师.主要研究方向为OFDM无线通信技术.E-mail:wuhong@nankai.edu.cn
- 基金资助:
- 国家自然科学基金 (No.61571244，No.61501262）; 天津市科技计划项目 (No.16YFZCSF00540）

FPGA Design of Real-Time Blind Source Separation for AIS Multi-cell Co-channel Signals

TANG Ran^1,2, WU Hong^1,2, ZHAO Ying-xin^1,2, MU Wei-wei^1,2, XU Xi-yan^1,2, MA Xiao-xu^1,2, LIU Bing^1,2, LIU Zhi-yang^1,2

1. College of Electronic Information and Optical Engineering, Nankai University, Tianjin 300350, China;
2. Tianjin Key Laboratory of Optoelectronic Sensor and Sensing Network Technology, Tianjin 300350, China

Received:2016-01-27 Revised:2016-05-11 Online:2017-09-25 Published:2017-09-25
- Supported by:
- National Natural Science Foundation of China (No.61571244, No.61501262); Science and Technology Project of Tianjin Municipality (No.16YFZCSF00540)

摘要/Abstract

摘要： 针对船舶自动识别系统（Automatic Identification System，AIS）中相邻多个小区的同频信号相互干扰、无法解调的问题，该文采用多天线接收混合信号，通过在FPGA上设计独立成分分析（Independent Component Analysis，ICA）算法来对混合信号进行实时盲分离.为满足实时性，文中用符号函数代替双曲正切函数对样点数据作非线性映射，简化迭代运算；并将样点数据分块存储，用于并行计算.同时实现了高精度特征分解（Eigen Value Decomposition，EVD），用于对混合数据进行白化.最后将设计的FPGA系统在Xilinx Isim中仿真，结果表明，主频20MHz时，系统在850μs内完成了从4路512点AIS混合信号中分离出了三路源信号.本文的设计也可应用于雷达、声纳等可能存在同频干扰的实时信号处理系统.

关键词: 多小区同频干扰, 多天线, 盲分离, 独立成分分析, 特征分解, FPGA

Abstract: In order to demodulate the mixed co-channel automatic identification system (AIS) signals from neighbor cells,a multi-antenna receiver system is employed where the FPGA based independent component analysis (ICA) algorithm is implemented to separate the mixtures.To achieve real-time processing,we simplify the iteration formula by using sign function instead of hyperbolic tangent for nonlinear mapping,reducing the hardware complexity.Furthermore,a parallel iteration structure is adopted to improve the real-time performance.The paper also designs high precision eigen value decomposition (EVD) module to whiten the received mixtures.Finally,the FPGA design is simulated in Xilinx software platform Isim.Simulation results show that,when clocked at 20 MHz,the system completes separating 4 channels of 512 points mixed AIS signals within 850 μ s.This design can also be applied in radar,sonar and other real-time processing systems where co-channel interference may exist.

Key words: multi-cell co-channel interference, multi-antenna, blind separation, independent component analysis, eigen decomposition, FPGA

中图分类号:

TP391

唐然, 吴虹, 赵迎新, 等. AIS多小区同频信号实时盲分离的FPGA设计[J]. 电子学报, 2017, 45(9): 2121-2126.

TANG Ran, WU Hong, ZHAO Ying-xin, et al. FPGA Design of Real-Time Blind Source Separation for AIS Multi-cell Co-channel Signals[J]. Acta Electronica Sinica, 2017, 45(9): 2121-2126.

参考文献

[1] 潘宝凤,梁先明.星载AIS接收系统设计及关键技术[J].电讯技术,2011,51(5):1-5. Pan Bao-feng,Liang Xian-min.Satellite-based AIS receiver system design and related key techniques[J].Telecommunication Engineering,2011,51(5):1-5.(in Chinese)
[2] Yang Meng-hui,Zou Yong-zhong,Fang Li.Collision and detection performance with three overlap signal collisions in space-based AIS reception[A].IEEE Conference on Trust,Security and Privacy in Computing and Communications[C].Liverpool,UK:IEEE,2012.1641-1648.
[3] Huang Wei-Chung,Huang Shao-Hang.FPGA implementation of 4-channel ICA for on-line EEG signal separation[A].IEEE Conference on Biomedical Circuits and Systems[C].Baltimore,MD,USA:IEEE,2008.65-68.
[4] Wang You-feng,Lin Qiu-hua.FPGA implementation of one-unit fixed-point ICA-R algorithm[A].International Conference on Intelligent Control and Information Processing[C].Dalian,China:IEEE,2010.191-194.
[5] Geethu R S,Krishna K M,George S N.Proposal for source separation of ground borne vibration signals and its FPGA implementation[A].International Conference on VLSI Systems,Architecture,Technology and Applications[C].Bangalore,India:IEEE,2015.1-5.
[6] Shiomi H,Fujio S,Okamura Y.Acceleration of FPGA-based ICA processor for real-time processing[A].2010 IEEE Antennas and Propagation Society International Symposium[C].Toronto,ON,Canada:IEEE,2010.1-4.
[7] Ranjith J,Muniraj N.FPGA implementation of optimized independent component analysis processor for biomedical application[A].International Conference on Computer Communication and Informatics[C].Coimbatore,India:IEEE,2013.1-5.
[8] Kim Chang-Min,Park Hyung-Min,Kim Taesu.FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling[J].IEEE Transactions on Neural Networks,2003,14(5):1038-1046.
[9] Aapo Hyvarinen.Fast and robust fixed-point algorithms for independent component analysis[J].IEEE Transactions on Neural Networks,1999,10(3):626-634.
[10] Aapo Hyvarinen,Juha Karhunen,Erkki Oja.独立成分分析[M].周宗谭,等,译.北京:电子工业出版社,2007.78-144.
[11] 张和发,李立萍,杨小牛.一种适用于微弱信号盲提取的白化方法[J].电子学报,2011,39(6):1297-1301. Zhang He-fa,Li li-ping,Yang Xiao-niu.An efficient whitening method for weak signal extraction[J].Acta Electronica Sinica,2011,39(6):1297-1301.(in Chinese)
[12] 阮宗利,李立萍,钱国兵.基于含噪复值ICA信号模型的快速不动点算法[J].电子与信息学报,2014,36(5):1094-1099. Ruan Zong-li,Li Li-ping,Qian Guo-bing.Fast fixed-point algorithm based on complex ICA signal model with noise[J].Journal of Electronics and Information Technology,2014,36(5):1094-1099.(in Chinese)
[13] 王少军,张启荣,彭宇.超越函数FPGA计算的最佳等距分段线性逼近方法[J].仪器仪表学报,2014,35(6):1209-1216. Wang Shao-jun,Zhang Qi-rong,Peng Yu.Optimal equidistant piecewise linear approximation algorithm for the computation of transcendental functions in FPGA[J].Chinese Journal of Scientific Instrument,2014,35(6):1209-1216.(in Chinese)
[14] 许乔,巩玉振,蔡惠智.基于FPGA的大矩阵奇异值分解的实现[J].电子测量技术,2014,37(6):68-72. Xu Qiao,Gong Yu-zhen,Cai Hui-zhi.Implementation to solve singular value decomposition of large matrix size in FPGAs[J].Electronic Measurement Technology,2014,37(6):68-72.(in Chinese)
[15] 张晓帆,李广军.基于低硬件复杂度、高速CORDIC的SVD模块设计与实现[J].电子学报,2015,43(4):738-742. Zhang Xiao-fan,Li Guang-jun.The design and implementation of SVD module with reduced hardware complexity and high-speed CORDIC processor[J].Acta Electronica Sinica,2015,43(4):738-742.(in Chinese)
[16] 祁艳杰,刘章发.基于Parallel CORDIC的高精度高速度直接数字频率合成器的FPGA实现[J].电子学报,2014,47(7):1392-1397. Qi Yan-jie,Liu Zhang-fa.FPGA implementation of high speed and high precision dircect digital frequency synthesizer based on parallel CORDIC[J].Acta Electronica Sinica,2014,47(7):1392-1397.(in Chinese)
[17] Coupe F G A.Digital frequency discriminator[J].Electronics Letters,1979,15(16):489-490.

AIS多小区同频信号实时盲分离的FPGA设计

FPGA Design of Real-Time Blind Source Separation for AIS Multi-cell Co-channel Signals

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

[1]	强幸子, 金翔, 张天骐. 基于相似度的NPLC-DSSS信号扩频码盲估计[J]. 电子学报, 2022, 50(8): 2043-2048.
[2]	袁海英, 曾智勇, 成君鹏. 面向灵活并行度的稀疏卷积神经网络加速器[J]. 电子学报, 2022, 50(8): 1811-1818.
[3]	陈晓杰, 李斌, 周清雷. RTL级可扩展高性能数据压缩方法实现[J]. 电子学报, 2022, 50(7): 1548-1557.
[4]	许皓文, 陆浩, 王振占. 高光谱微波辐射计系统中2GHz带宽数字谱仪设计[J]. 电子学报, 2022, 50(6): 1472-1479.
[5]	曲立国, 陈国豪, 胡俊, 陈鹏. 单次扫描连通域分析算法研究综述[J]. 电子学报, 2022, 50(6): 1521-1536.
[6]	刘胜, 王帮民, 张兰勇. 多通道盲电磁辐射现场分离方法研究[J]. 电子学报, 2022, 50(3): 557-566.
[7]	王鹏, 邹彬, 刘金枝, 周丹阳. 基于Xilinx型FPGA系统单粒子效应评估方法研究[J]. 电子学报, 2022, 50(11): 2716-2721.
[8]	李斌, 齐延荣, 周清雷. 基于Winograd算法的目标检测加速器设计与优化[J]. 电子学报, 2022, 50(10): 2387-2397.
[9]	蔡莹, 朱翔, 王舰, 李昊远, 韩建伟. 基于激光注入的FPGA加密防护设计验证研究[J]. 电子学报, 2022, 50(10): 2381-2386.
[10]	张建民, 黎铁军, 马柯帆, 肖立权. 一种加速FPGA布线的不可满足子式求解算法[J]. 电子学报, 2021, 49(6): 1210-1216.
[11]	刘杰, 葛一凡, 田明, 马力强. 基于ZYNQ的可重构卷积神经网络加速器[J]. 电子学报, 2021, 49(4): 729-735.
[12]	孙明乾, 乔庐峰, 陈庆华. 一种无匹配时间损耗的DFA压缩算法的研究与实现[J]. 电子学报, 2020, 48(6): 1132-1139.
[13]	刘秋红, 许漫坤, 李天昀, 陆明明. 基于互补对称滤波器的APCMA信号的盲分离算法[J]. 电子学报, 2020, 48(12): 2394-2401.
[14]	蹇强, 张培勇, 王雪洁. 一种可配置的CNN协加速器的FPGA实现方法[J]. 电子学报, 2019, 47(7): 1525-1531.
[15]	刘公绪, 史凌峰, 辛东金. 基于FPGA的零误差大数阶乘算法的设计与实现[J]. 电子学报, 2019, 47(5): 1180-1184.