纳米级CMOS集成电路的单粒子效应及其加固技术

doi:10.3969/j.issn.0372-2112.2018.10.027

电子学报 ›› 2018, Vol. 46 ›› Issue (10): 2511-2518.DOI: 10.3969/j.issn.0372-2112.2018.10.027

纳米级CMOS集成电路的单粒子效应及其加固技术

赵元富, 王亮, 岳素格, 孙永姝, 王丹, 刘琳, 刘家齐, 王汉宁

北京微电子技术研究所, 北京 100076

收稿日期:2016-12-19 修回日期:2017-09-09 出版日期:2018-10-25
- 作者简介:
- 赵元富,男,1962年生于江西省进贤县,研究员,博士生导师.主要研究方向为抗辐射加固集成电路设计技术;王亮,男,1981年生于黑龙江省五常市,高级工程师.主要研究方向为集成电路的抗辐射加固设计技术.E-mail:wangliang150200@163.com
- 基金资助:
- 国家自然科学基金 (No.61674015，No.11690045）

Single Event Effect and its Hardening Technique in Nano-scale CMOS Integrated Circuits

ZHAO Yuan-fu, WANG Liang, YUE Su-ge, SUN Yong-shu, WANG Dan, LIU Lin, LIU Jia-qi, WANG Han-ning

Beijing Microelectronics Technology Insitute, Beijing 100076

Received:2016-12-19 Revised:2017-09-09 Online:2018-10-25 Published:2018-10-25

摘要/Abstract

摘要： 空间应用的集成电路受到辐射效应的影响，会出现瞬态干扰、数据翻转、性能退化、功能失效甚至彻底毁坏等问题.随着器件特征尺寸进入到100nm以下（以下简称纳米级），这些问题的多样性和复杂性进一步增加，单粒子效应成为集成电路在空间可靠性应用的主要问题，给集成电路的辐射效应评估和抗辐射加固带来了诸多挑战.本文以纳米级CMOS集成电路为研究对象，结合近年来国内外的主要技术进展，介绍研究团队在65nm集成电路单粒子效应和加固技术方面的研究成果，包括首次提出的单粒子时域测试和分析方法、单粒子多节点翻转加固方法和单粒子瞬态加固方法等.

关键词: 集成电路, 纳米级, 单粒子效应, 抗辐射加固

Abstract: The integrated circuits used in aerospace can be influenced by space radiation effects, leading to some problems such as transient disturbance, data upset, performance degradation, functional failure or even destructive damage. The variety and complexity of these problems increases as the feature size of devices scales down to less than 100 nm (called as "nano-scale" in this paper). Single event effect has become a main reliability factor for space-used ICs, and brought about much challenge to radiation hardness assurance and radiation hardening. Taking nano-scale ICs as the research object, combined with recent technology progress, this paper introduces the research achievements in single event effect and hardening techniques of 65 nm ICs, including the proposed time-domain testing and analyzing method, radiation hardening techniques for single event multi-node upsets and single event transients.

Key words: integrated circuit, nano-scale, single event effect, radiation hardening

中图分类号:

TN43

赵元富, 王亮, 岳素格, 孙永姝, 王丹, 刘琳, 刘家齐, 王汉宁. 纳米级CMOS集成电路的单粒子效应及其加固技术[J]. 电子学报, 2018, 46(10): 2511-2518.

ZHAO Yuan-fu, WANG Liang, YUE Su-ge, SUN Yong-shu, WANG Dan, LIU Lin, LIU Jia-qi, WANG Han-ning. Single Event Effect and its Hardening Technique in Nano-scale CMOS Integrated Circuits[J]. Acta Electronica Sinica, 2018, 46(10): 2511-2518.

参考文献

[1] Robert Ecoffet.On-Orbit Anomalies:Investigations and Root Cause Determination[M].Las Vegas:IEEE NSREC Short Course,2011.
[2] G E Moore.Cramming more components onto integrated circuits[J].Electronics,1965,38(8):114~117.
[3] Suge Yue,et al.Modeling and simulation of single-event effect in CMOS circuit[J].Journal of Semiconductors,2015,36(11):111002-1-10.
[4] C Inguimbert,et al.Electron induced SEUs:Micro-dosimetry in nano-metric volumes[J].IEEE Trans Nucl Sci,2015,62(6):2846-2852.
[5] Robert Baumann.Single-Event Effects in Advanced CMOS Technology[M].Seattle:IEEE NSREC Short Course,2005.
[6] Kenneth P Rodbell,et al.Low-energy proton-induced single-event upsets in 65 nm node,silicon-on-insulator,latches and memory cells[J].IEEE Trans Nucl Sci,2007,54(6):2474-2479.
[7] M P King,et al.Electron-induced single event upsets in static random access memory[J].IEEE Trans Nucl Sci,2013,60(6):4122-4129.
[8] Matthew J Gadlage,et al.Electron-induced single-event upsets in 45-nm and 28-nm Bulk CMOS SRAM-Based FPGAs operating at nominal voltage[J].IEEE Trans Nucl Sci,2015,62(6):2717-2724.
[9] Philippe Roche,et al.SEE and TID Radiation Test Results of Digital Circuits Designed and Manufactured in ST 40nm/45nm/65nm/90nm/130nm CMOS Technologies[R].Crolles:European Space Agency,2011.
[10] David L Hansen,et al.Clock,flip-flop,and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology[J].IEEE Trans Nucl Sci,2009,56(6):3542-3550.
[11] 罗尹红,等.纳米静态随机存储器低能质子单粒子翻转敏感性研究[J].物理学报,2016,65(6):068501-1-068501-10. Luo Yin-Hong et al.Single event upsets sensitivity of low energy proton in nanometer static random access memory[J].Acta Physica Sinica,2016,65(6):068501-1-10.(in Chinese)
[12] Oluwole A Amusan,et al.Charge clloction and charge sharing in a 130 nm CMOS technology[J].IEEE Trans Nucl Sci,2006,53(6):3253-3258.
[13] Lin Liu,et al.3D Simulation of charge collection and MNU in SEU hardened storage cells[A].2009 RADECS Proceeding[C].Bruges:RADECS,2009.230-234.
[14] S E Diehl,et al.Considerations for single event immune VLSI logic[J].IEEE Trans Nucl Sci,1983,30(6):4501-4507.
[15] Arthur L F,et al.Single event upset in combinatorial and sequential current mode logic[J].IEEE Trans Nucl Sci,1985,32(6):4216-4218.
[16] Matthew J Gadlage,et al.Increased single-event transient pulsewidths in a 90-nm bulk CMOS technology operating at elevated temperatures[J].IEEE Trans Device Mater Rel,2010,10(1):157-163.
[17] Jonathan R Ahlbin,et al.Single-event transient pulse quenching in advanced CMOS logic circuits[J].IEEE Trans Nucl Sci,2009,56(6):3050-3056.
[18] Suge Yue,et al.Single event transient pulse width measurement of 65nm bulk CMOS circuits[J].Journal of Semiconductors,2015,36(11):115006-1-4.
[19] Lin Liu,et al.The 65nm double-DICE storage element based on error-quenching layout design to reduce single-event multiple node upsets[A].2016 RADECS Proceeding[C].Bremen:RADECS,2016.1-6.
[20] Yuanfu Zhao,et al,SEU and SET of 65nm bulk CMOS flip-flops and their implications for RHBD[J].IEEE Trans Nucl Sci,2015,62(6):2666-2672.
[21] Xinyuan Zhao,et al.Single event transients of scan flip-flop and an SET-immune redundant delay filter (RDF)[A].RADECS,2013[A].2013 RADECS Proceeding[C].Oxford:RADECS,2013.1-5.

纳米级CMOS集成电路的单粒子效应及其加固技术

Single Event Effect and its Hardening Technique in Nano-scale CMOS Integrated Circuits

PDF

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

[1]	赵毅强, 高雅, 马浩诚, 张启智, 叶茂, 夏显召, 何家骥. 软件定义主动屏蔽层生成及防护技术研究[J]. 电子学报, 2022, 50(6): 1381-1388.
[2]	文溢, 陈建军, 梁斌, 池雅庆, 黄俊. 28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究[J]. 电子学报, 2022, 50(11): 2653-2658.
[3]	刘耿耿, 李泽鹏, 郭文忠, 陈国龙, 徐宁. 面向超大规模集成电路物理设计的通孔感知的并行层分配算法[J]. 电子学报, 2022, 50(11): 2575-2583.
[4]	左小寒, 梁华国, 倪天明, 杨兆, 束月, 蒋翠云, 鲁迎春. 基于间隔分组的TSV聚簇故障冗余结构[J]. 电子学报, 2021, 49(4): 805-811.
[5]	黄正峰, 潘尚杰, 曹剑飞, 宋钛, 欧阳一鸣, 梁华国, 倪天明, 鲁迎春. 32nm CMOS工艺三点翻转自恢复锁存器设计[J]. 电子学报, 2021, 49(2): 394-400.
[6]	唐跞, 丁满来, 王雪梅, 曲佳萌, 温智磊. 一种基于电荷泵锁相环的高精度数字移相方法[J]. 电子学报, 2020, 48(12): 2331-2337.
[7]	于浩, 郭裕顺, 李康. 基于g_m/I_d参数的CMOS运算放大器设计重用方法[J]. 电子学报, 2019, 47(8): 1626-1632.
[8]	史淑廷, 郭刚, 刘建成, 蔡莉, 陈泉, 沈东军, 惠宁, 张艳文, 覃英参, 韩金华, 陈启明, 张付强, 殷倩, 肖舒颜. 半导体器件内离子有效LET值测量方法研究[J]. 电子学报, 2018, 46(10): 2546-2550.
[9]	李雄伟, 王晓晗, 张阳, 陈开颜, 徐璐. 一种基于核最大间距准则的硬件木马检测新方法[J]. 电子学报, 2017, 45(3): 656-661.
[10]	雷才洪. 单片CDCTA-C低功耗电控调谐双模式三阶正交振荡器的设计[J]. 电子学报, 2017, 45(3): 599-604.
[11]	欧阳一鸣, 孙成龙, 陈奇, 梁华国, 易茂祥, 黄正峰, 闫爱斌. 3D NoC关键通信部件容错方法研究综述[J]. 电子学报, 2016, 44(12): 3053-3063.
[12]	余旭明, 洪伟, 王维波, 张斌. Ku波段宽带氮化镓功率放大器MMIC[J]. 电子学报, 2015, 43(9): 1859-1863.
[13]	李迪, 杨银堂, 石佐辰, 柳扬. 一种适用于IEEE802.15.4(ZigBee)标准的2.4GHz CMOS射频收发机设计[J]. 电子学报, 2015, 43(5): 1021-1027.
[14]	常郝, 梁华国, 蒋翠云, 欧阳一鸣, 徐辉. 一种3D堆叠集成电路中间绑定测试时间优化方案[J]. 电子学报, 2015, 43(2): 393-398.
[15]	张鹏, 王新成, 周庆. 基于电磁辐射信号分析的芯片硬件木马检测[J]. 电子学报, 2014, 42(2): 341-346.