基于DFT滤波器组的低时延FPGA语音处理实现研究

doi:10.3969/j.issn.0372-2112.2018.03.027

电子学报 ›› 2018, Vol. 46 ›› Issue (3): 695-701.DOI: 10.3969/j.issn.0372-2112.2018.03.027

基于DFT滤波器组的低时延FPGA语音处理实现研究

薛一鸣¹, 陈鹞¹, 何宁宁², 胡彩娥³, 王建平¹

1. 中国农业大学信息与电气工程学院, 北京 100083;
2. 北京中电华大电子设计有限责任公司, 北京 102209;
3. 国网北京市电力公司, 北京 100031

收稿日期:2017-01-03 修回日期:2017-11-26 出版日期:2018-03-25
- 作者简介:
- 薛一鸣,男,1968年出生,山西文水人.中国农业大学信息与电气工程学院副教授、硕士生导师.主要研究方向为多媒体信息处理、多媒体信息安全、大规模集成电路设计.E-mail:xueym@cau.edu.cn;陈鹞,男,1992年6月出生,江西上饶人.现为中国农业大学信息与电气工程学院硕士研究生,从事信息与通信工程相关研究.E-mail:chenyao@cau.edu.cn;何宁宁,男,1994年6月出生,浙江丽水人.现为北京中电华大电子设计有限责任公司数字电路设计工程师,从事算法实现与数字电路设计相关研究.E-mail:henn@hed.com.cn
- 基金资助:
- 国家自然科学基金 (No.U1536121）

DFT Filter Bank-Based Realization of Low Delay Speech Processing on FPGA

XUE Yi-ming¹, CHEN Yao¹, HE Ning-ning², HU Cai-e³, WANG Jian-ping¹

1. College of Information and Electrical Engineering, China Agricultural University, Beijing 100083, China;
2. CEC Huada Electronic Design Co., Ltd, Beijing 102209, China;
3. State Grid Beijing Electric Power Company, Beijing 100031, China

Received:2017-01-03 Revised:2017-11-26 Online:2018-03-25 Published:2018-03-25
- Supported by:
- National Natural Science Foundation of China (No.U1536121)

摘要/Abstract

摘要： 提出了WOLA（Weighted Overlap-Add）并行结构的低时延DFT滤波器组的设计和FPGA实现方法.为降低系统总体时延，在综合考虑传递失真、混迭失真的基础上，将群时延引入系统目标函数，并采用非对称综合原型滤波器设计方法，提出迭代算法，实现了DFT滤波器组低时延优化设计.通过对DFT滤波器组中分析和综合功能的关键模块采用多路并行乘法、多级流水加法链设计，实现了并行的WOLA结构DFT滤波器组，降低FPGA实现的计算时延.整个设计在Xilinx公司的Zynq7020型号FPGA芯片上进行实现.PESQ测试表明，设计的DFT滤波器组能取得较好的语音质量.与串行WOLA结构的实现对比表明，在16kHz语音采样率下，并行的WOLA结构FPGA实现的总时延能降低1.192ms，其中群时延降低12%，计算时延降低29.2%.

关键词: 语音处理, DFT滤波器组, 低时延, FPGA, 并行设计

Abstract:

A low-latency parallel WOLA (Weighted Overlap-add) DFT filter bank design method and its implementation on FPGA are presented. System objective function combined with group delay, asymmetric synthesis window design and iterative algorithm are adopted to reduce the overall system delay during the optimization of DFT filter banks. Calculation delay of FPGA implementation is controlled through multichannel parallel multiplication, multistage pipeline addition chain in key modules of DFT filter banks. The whole design is implemented on a Xilinx FPGA chip of Zynq7020. PESQ test shows that the design can achieve good speech quality. Compared with the serial WOLA structure, the delay of parallel WOLA can be reduced by 1. 192 ms at 16 kHz speech sampling rate, with the group delay reduced by 12% and the calculation delay reduced by 29. 2%.

Key words: speech processing, DFT filter bank, low delay, FPGA, parallel design

中图分类号:

TN912.3

薛一鸣, 陈鹞, 何宁宁, 等. 基于DFT滤波器组的低时延FPGA语音处理实现研究[J]. 电子学报, 2018, 46(3): 695-701.

XUE Yi-ming, CHEN Yao, HE Ning-ning, et al. DFT Filter Bank-Based Realization of Low Delay Speech Processing on FPGA[J]. Acta Electronica Sinica, 2018, 46(3): 695-701.

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基于DFT滤波器组的低时延FPGA语音处理实现研究

DFT Filter Bank-Based Realization of Low Delay Speech Processing on FPGA

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