28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究

doi:10.12263/DZXB.20211691

电子学报 ›› 2022, Vol. 50 ›› Issue (11): 2653-2658.DOI: 10.12263/DZXB.20211691

28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究

文溢, 陈建军, 梁斌, 池雅庆, 黄俊

国防科技大学计算机科学学院，湖南长沙 410073

收稿日期:2021-12-23 修回日期:2022-07-09 出版日期:2022-11-25
- 作者简介:
- 文溢　男，1992年3月生，湖南长沙人.现为国防科技大学计算机学院微电子所工程师.主要从事集成电路设计与抗辐照加固设计等方面的研究工作.E-mail: wenyi19920312@126.com
  陈建军（通讯作者）　男，1983年10月生，贵州毕节人.博士毕业于国防科技大学电子科学与技术专业，现任国防科技大学计算机学院研究生导师，主要研究方向为高速通信系统和集成电路设计的抗辐照加固技术.
  梁斌　男，1979年7月生，湖南常德人.博士毕业于国防科技大学电子科学与技术专业，现任国防科技大学计算机学院研究生导师，主要研究方向为高速通信系统和集成电路设计的抗辐照加固技术.E-mail: liangbin110@126.com
  池雅庆　男，1982年2月生，重庆沙坪坝人.博士毕业于国防科技大学电子科学与技术专业，现任国防科技大学计算机学院研究生导师，主要研究方向为高速通信系统和集成电路设计的抗辐照加固技术.E-mail: yqchi@nudt.edu.cn
  黄俊　女，1991年10月生，湖南长沙人.现为国防科技大学计算机学院微电子所工程师.主要从事集成电路设计与抗辐照加固设计等方面的研究工作.E-mail: 654302416@qq.com
- 基金资助:
- 国家自然科学基金 (61974163); 国防科技大学高层次创新人才培训计划项目 (4142D125106)

Research on Single-Event Radiation Characteristics of an 8-Gbps SerDes in a 28nm CMOS Technology

WEN Yi, CHEN Jian-jun, LIANG Bin, CHI Ya-qing, HUANG Jun

College of Computer Science，National University of Defense Technology，Changsha，Hunan 410073，China

Received:2021-12-23 Revised:2022-07-09 Online:2022-11-25 Published:2022-11-19

摘要/Abstract

摘要：

本文研究了28nm体硅CMOS工艺下8-Gbps通用结构高速并转串/串转并接口（Serializer/Deserializer，SerDes）的单粒子辐射特性，该SerDes由电压模发送器（Transmitter，TX）和相位插值（Phase Interpolation，PI）型接收器（Receiver，RX）组成，通过双指数电流源对整个SerDes的TX和RX进行了单粒子效应仿真，仿真结果表明该SerDes的TX和RX均会发生单粒子瞬态（Single-Event Transient，SET），且主要敏感节点包括：D触发器，采样器和时钟相位插值器.进一步采用脉冲激光对整个SerDes进行了扫描测试，测试结果验证了仿真结论.该研究为抗辐射SerDes的研制提供了重要的理论依据.

关键词: 串转并/并转串接口, 单粒子效应, 双指数电流源仿真, 敏感节点, 脉冲激光测试

Abstract:

In this paper, single-event radiation characteristics of an 8-Gbps high-speed Serializer/Deserializer interface(SerDes) is studied in a 28nm bulk CMOS technology. The SerDes, which is composed of a voltage mode transmitter(TX) and a phase interpolating(PI) receiver(RX), is simulated by a double exponential current source to find the sensitive node, and the simulation results show both the TX and RX appear single-event transient(SET) and the main sensitive nodes of the whole SerDes include D flip-flop, samplers and clock phase interpolators. These sensitive nodes are further verified through pulsed-laser single-event experiment, and the study provides an important theoretical basis for the design of radiation-hardened SerDes.

Key words: serializer/deserializer interface, single-event effect, double exponential current source simulation, sensitive node, pulse-laser experiments

中图分类号:

TN402

文溢, 陈建军, 梁斌, 等. 28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究[J]. 电子学报, 2022, 50(11): 2653-2658.

Yi WEN, Jian-jun CHEN, Bin LIANG, et al. Research on Single-Event Radiation Characteristics of an 8-Gbps SerDes in a 28nm CMOS Technology[J]. Acta Electronica Sinica, 2022, 50(11): 2653-2658.

图/表 13

图1 SerDes原理图

图2 单粒子仿真testbench示意图

图3 TX模拟单粒子效应仿真结果

图4 D触发器电路结构

图5 D触发器发生SET时D、A、Q节点输出波形

图6 RX模拟单粒子效应仿真结果

图7 采样器电路结构

图8 采样器发生SET时输入输出节点波形

图9 PI电路结构

图10 PI发生SET输出波形

图11 测试系统

图12 TX激光测试发生SET和SEFI的瞬态波形

表1 RX激光测试误码分布

模块	子模块	误码个数
RX	AFE	0
	DFE	15345
	S2P	24652
	CDR	7897

参考文献 15

1	ARMSTRONG S E, OLSON B D, POPP J, et al. Single-event transient error characterization of a radiation-hardened by design 90nm SerDes transmitter driver[J]. IEEE Transactions on Nuclear Science, 2009, 56(6): 3463-3468.
2	ARMSTRONG S E, OLSON B D, HOLMAN W T, et al. Demonstration of a differential layout solution for improved ASET tolerance in CMOS A/MS circuits[J]. IEEE Transactions on Nuclear Science, 2010, 57(6): 3615-3619.
3	YUAN H Z, CHEN J J, LIANG B, et al. An SEU/SET-tolerant phase frequency detector with double loop self-sampling technology for clock data recovery[J]. IEEE Transactions on Nuclear Science, 2019, 66(7): 1483-1490.
4	YUAN H Z, CHEN J J, LIANG B, et al. Fault-tolerant multi-node coupling triple mode redundancy voltage controlled oscillator for reducing soft error in clock and data recovery[J]. Electronics Letters, 2019, 55(5): 250-251.
5	YUAN H Z, GUO Y, CHEN J J, et al. 28 nm fault-tolerant hardening-by-design frequency divider for reducing soft errors in clock and data recovery[J]. IEEE Access, 2019, 7: 47955-47961.
6	ZANCHI Z, BUCHNER S, HAFER C, et al. Investigation and mitigation of analog SET on a bandgap reference in triple-well CMOS using pulsed laser techniques[J]. IEEE Transactions on Nuclear Science, 2011, 58(6): 2570-2577.
7	ZHAO Q F, YANG G Q, SUN Y J, et al. Research on the effect of single-event transient of an on-chip linear voltage regulator fabricated on 130 nm commercial CMOS technology[J]. Microelectronics Reliability, 2017, 73: 116-121.
8	SAVOJ J, RAZAVI B. A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector[J]. IEEE Journal of Solid-State Circuits, 2001, 36(5): 761-768.
9	TAN J W, GUO Y, CHEN J J, et al. A state recovery design against single-event transient in high-speed phase interpolation clock and data recovery circuit[C]//CHEN M H. 2017 IEEE 12th International Conference on ASIC. Guiyang: IEEE, 2017: 339-342.
10	YUAN H Z, CHEN J J, LIANG B, et al. A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath-current-releasing technology[C]//CHEN M H. Proceedings of International Conference on ASIC, 2017 IEEE 12th International Conference on ASIC. Guiyang: IEEE, 2017: 241-244.
11	ZHENG X Q, ZHANG C, LV F X, et al. A 40-Gb/s quarter-rate SerDes transmitter and receiver chipset in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2017, 52(11): 2963-2978.
12	IM J, FREITAS D, ROLDAN A B, et al. A 40-to-56 Gb/s PAM-4 receiver with ten-tap direct decision-feedback equalization in 16-nm FinFET[J]. IEEE Journal of Solid-State Circuits, 2017, 52(12): 3486-3502.
13	HAO P P, CHEN S M, WU Z Y, et al. On-chip relative single-event transient/single-event upset susceptibility test circuit for integrated circuits working in real time[J]. IEEE Transactions on Device and Materials Reliability, 2018, 65(1): 376-381.
14	GUO S, LI J, GUI P, et al. Single-event transient effect on a self-biased ring-oscillator PLL and an LC PLL fabricated in SOS technology[J]. IEEE Transactions on Nuclear Science, 2013, 60(6): 4668-4672.
15	HAO P P, CHEN S M. Single-event transient susceptibility analysis and evaluation methodology for clock distribution network in the integrated circuit working in real time[J]. IEEE Transactions on Device and Materials Reliability, 2017, 17(3): 539-548.

[1]	史淑廷, 郭刚, 刘建成, 蔡莉, 陈泉, 沈东军, 惠宁, 张艳文, 覃英参, 韩金华, 陈启明, 张付强, 殷倩, 肖舒颜. 半导体器件内离子有效LET值测量方法研究[J]. 电子学报, 2018, 46(10): 2546-2550.
[2]	赵元富, 王亮, 岳素格, 孙永姝, 王丹, 刘琳, 刘家齐, 王汉宁. 纳米级CMOS集成电路的单粒子效应及其加固技术[J]. 电子学报, 2018, 46(10): 2511-2518.
[3]	贺朝会;耿斌;杨海亮;陈晓华;李国政;王燕萍. 浮栅ROM与SRAM的辐射效应比较分析[J]. 电子学报, 2003, 31(8): 1260-1262.

28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究

Research on Single-Event Radiation Characteristics of an 8-Gbps SerDes in a 28nm CMOS Technology

RichHTML

PDF

可视化

摘要/Abstract

引用本文

使用本文

图/表 13

参考文献 15

相关文章 3

编辑推荐

Metrics