Terahertz detection and imaging technology are the foundation and key to promote terahertz technology development. In order to realize high sensitivity terahertz detection and imaging, a mesa-type silicon-based blocked-impurity-band (BIB) terahertz detector is designed. The structure and detection mechanism of the detector are introduced in detail. The preparation processes are presented briefly. A series of its photoelectric performances are investigated. A blackbody responsivity test system is built. The results show that at 4.2K temperature and 3.8V bias, its peak responsivity reaches 55A/W, and the response spectrum covers the frequency range from 6.7~60THz. In addition, a scan imaging system is set, and the high-resolution passive imaging is achieved. The imaging result shows that the spatial resolution and the temperature resolution of the imaging system can reach about 400μm and 7.5mK, respectively.

Silicon-based phototransistors have broad application prospects in the fields of high-frequency communication, automatic control, and power systems. From the perspective of system verification and simulation, there is an urgent need to establish an equivalent circuit model of phototransistors, which needs to include electrical and optical characteristics. This paper proposes a SPICE equivalent model of high-frequency(100MHz~1GHz) silicon-based phototransistors, including the main photoelectric characteristics of the device, and the extraction method of key electrical and optical parameters in the model is established by TCAD simulation. Based on the established SPICE model equivalent circuit of the high-frequency phototransistor, the simulation results can fully describe the electrical and optical characteristics of the phototransistor, it shows that the SPICE model and parameter extraction method proposed in this paper have reference value for system simulation based on high-frequency phototransistor.

A MOS-like low operating voltage gate-controlled silicon-based light-emitting device is designed and fabricated using 0.18μm standard CMOS technology. The light emitting device adapts a n⁺-p⁺-p⁺-n⁺-p⁺-p⁺-n⁺ interdigital structure, in which a poly-Si gate between two adjacent p⁺ regions working as a third-terminal control electrode was designed. The poly-Si gate is used to produce field-induced junctions at the edge of source/drain region, so as to decrease the breakdown voltage of p⁺/n-well junction and increase optical power of the device. The measured results indicate that the device can emit yellow visible light with wavelength from 420nm to 780nm. Under forward gate voltage of 3V, the breakdown voltage of p⁺/n-well junction can be reduced to below 3V, and the optical power can be increased to more than twice. Because of its low operating voltage and full compatibility with CMOS technology, the device can be integrated with other CMOS circuits by using a single power supply, which has certain applications in the field of silicon-based optoelectronic integration.

The yield of the Through-Silicon-Vias (TSVs)-based Three-Dimensional Integrated Circuits (3D ICs) is limited by the clustered faults due to immature manufacturing processes and aging. To tolerate TSV clustered faults, a redundancy architecture based on grouping at intervals is demonstrated in this paper. Owing to the use of grouping at intervals, the clustered TSV faults can be dispersed into different redundant groups and repaired with their own repair sources. Besides, MUX chains are utilized to realize the sharing of all repair sources. In experiments, compared with the previous router-based, ring-based and shift-switch redundancy architecture, the repair rates of proposed architecture are enhanced to 27.5%, 62.7% and 11.4%, respectively. More importantly, the repair rate remains close to 100% in severely clustered situation.

Based on CRRC silicon carbide (SiC) process technology platform, 1200V high capacity SiC metal-oxide semiconductor field-effect transistor (MOSFET) device has been fabricated by adopting ion-implanted JFET region, the optimal termination design, gate bus-bar design and gate oxidation process. The fabricated SiC MOSFET is based on a planar gate structure. The test results show that the gate breakdown voltage of the device is above 55V and it achieves a relatively lower interface state density. At room temperature, the threshold voltage of the device is 2.7V. The maximum blocking voltage and the output current capability of fabricated SiC MOSFET is up to 1600V and 50A, respectively. At 175℃, the threshold voltage shift is less than 0.8V, and the gate leakage current of the device is less than 45nA when the gate voltage is 20V. All of the results show that the fabricated SiC MOSFET has superior electrical characteristics. It occupies a potential in high temperature and high power applications.

The failure models of SiC JFET and SiC MOSFET have been developed.Based on the conventional circuit models of SiC JFET and SiC MOSFET,the additional leakage currents between the electrodes are introduced.For SiC JFET,the leakage current between the drain and the source is considered.For SiC MOSFET,two leakage currents are considered,one is the current between the drain and the source,another is the additional leakage current of the gate.Furthermore,the mobility dependent on the temperature and the electric-field strength replaces the constant mobility in conventional circuit models.The results from other experimental works and TCAD simulations verify the failure models of SiC JFET and SiC MOSFET.The developed failure models can be used to compare the short-circuit performances of SiC JFET and SiC MOSFET.

The asymmetrical double-material-gate s-Si (strained Silicon) HALO doping channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure is proposed. The front gate and back gate are composed of two metals with different work functions. It has the higher doping concentration in the HALO doping channel end near the drain. The two-dimensional Poisson's equation is solved by applying the parabolic potential approximation and the suitable boundary condition. The analytical models of surface potential、 surface electric field and threshold voltage for the double-material-gate device are constructed by solving which of the front gate and back gate. Results show that the proposed novel device is expected to suppress the short channel effect、hot carrier effect and drain induced barrier lowering. The derived analytical models accord with the DESSIS simulation results very well.